CLK_DIV_LEFTBUS_VAL (reference) in projects: arch

Searched refs:CLK_DIV_LEFTBUS_VAL (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-exynos/
A D	clock_init_exynos4.c	`65 writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus); in system_clock_init()`
A D	exynos4_setup.h	`146 #define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) \| (GDL_RATIO)) macro`

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