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Searched refs:CLOCK_ID_XCPU (Results 1 – 16 of 16) sorted by relevance

/arch/arm/mach-tegra/tegra20/
A Dwarmboot_avp.h14 #define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
A Dclock.c607 return CLOCK_ID_XCPU; in clk_id_to_pll_id()
800 case CLOCK_ID_XCPU: in clock_get_simple_pll()
/arch/arm/mach-tegra/
A Dcpu.h53 #define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
A Dclock.c800 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU); in clock_init()
815 debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]); in clock_init()
A Dcpu.c216 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; in pllx_set_rate()
/arch/arm/include/asm/arch-tegra20/
A Dclock-tables.h24 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, enumerator
/arch/arm/include/asm/arch-tegra114/
A Dclock-tables.h23 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, enumerator
/arch/arm/include/asm/arch-tegra30/
A Dclock-tables.h23 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, enumerator
/arch/arm/mach-tegra/tegra114/
A Dcpu.c59 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; in enable_cpu_clocks()
A Dclock.c678 return CLOCK_ID_XCPU; in clk_id_to_pll_id()
780 case CLOCK_ID_XCPU: in clock_get_simple_pll()
/arch/arm/include/asm/arch-tegra124/
A Dclock-tables.h24 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, enumerator
/arch/arm/mach-tegra/tegra124/
A Dcpu.c52 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; in enable_cpu_clocks()
A Dclock.c861 return CLOCK_ID_XCPU; in clk_id_to_pll_id()
1198 case CLOCK_ID_XCPU: in clock_get_simple_pll()
/arch/arm/include/asm/arch-tegra210/
A Dclock-tables.h24 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, enumerator
/arch/arm/mach-tegra/tegra30/
A Dclock.c662 return CLOCK_ID_XCPU; in clk_id_to_pll_id()
884 case CLOCK_ID_XCPU: in clock_get_simple_pll()
/arch/arm/mach-tegra/tegra210/
A Dclock.c948 return CLOCK_ID_XCPU; in clk_id_to_pll_id()
1280 case CLOCK_ID_XCPU: in clock_get_simple_pll()

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