| /arch/arm/mach-keystone/include/mach/ |
| A D | clock-k2hk.h | 38 #define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2}
39 #define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4}
40 #define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
41 #define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}
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| /arch/mips/mach-mscc/ |
| A D | Kconfig | 65 bool "Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16)"
71 bool "Hynix H5TQ1G63BFA (1Gbit DDR3, x16)"
74 bool "Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16)"
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| /arch/arm/dts/ |
| A D | stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi | 9 * DDR type / Platform DDR3/3L
12 * datasheet 0 = W631GU6MB15I / DDR3-1333
19 #define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz"
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| A D | stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 8 * DDR type: DDR3 / DDR3L
18 #define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz"
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| A D | stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 8 * DDR type: DDR3 / DDR3L
18 #define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000kHz"
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| A D | stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi | 8 * DDR type: DDR3 / DDR3L
18 #define DDR_MEM_NAME "DDR3-DDR3L 32bits 528000kHz"
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| A D | stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi | 9 * DDR type / Platform DDR3/3L
12 * datasheet 0 = W631GU6MB15I / DDR3-1333
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| A D | stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi | 9 * DDR type / Platform DDR3/3L
12 * datasheet 0 = W632GU6NB15I / DDR3-1333
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| A D | stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi | 9 * DDR type / Platform DDR3/3L
12 * datasheet 0 = W634GU6NB15I / DDR3-1333
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| A D | armada-3720-db.dts | 4 * (DB-88F3720-DDR3)
20 model = "Marvell Armada 3720 Development Board DB-88F3720-DDR3";
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| A D | armada-3720-uDPU.dtsi | 4 * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
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| /arch/mips/mach-mtmips/mt7621/ |
| A D | Kconfig | 51 prompt "DDR3 timing parameters"
86 The board can be configured with DDR2 (64MiB~256MiB) or DDR3
96 The board can be configured with DDR2 (64MiB~256MiB) or DDR3
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| /arch/arm/mach-sunxi/ |
| A D | Kconfig | 614 bool "DDR3 1333"
643 which use a DDR3-1333 timing.
667 which use a DDR3-1333 timing.
716 Set the dram type, 3: DDR3, 7: LPDDR3
732 (for DDR3-1600) are 312 to 792.
809 Select the timings of the DDR3 chips.
817 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
824 that down binning to DDR3-1066F is supported (because DDR3-1066F
825 uses a bit faster timings than DDR3-1333H).
828 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
[all …]
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| A D | dram_sun8i_a83t.c | 445 #error Unsupported DRAM type, Please set DRAM type (3:DDR3, 7:LPDDR3) in sunxi_dram_init()
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| /arch/arm/mach-mvebu/ |
| A D | kwbimage.cfg.in | 25 # Include U-Boot SPL with DDR3 training code into Binary Header
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| /arch/arm/include/asm/arch-rockchip/ |
| A D | sdram.h | 11 DDR3 = 3, enumerator
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| /arch/arm/mach-mediatek/ |
| A D | Kconfig | 26 including NEON and GPU, Mali-450 graphics, several DDR3 options,
38 including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
111 chip and several DDR3 and DDR4 options.
120 chip and several DDR3 and DDR4 options.
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| /arch/arm/mach-airoha/ |
| A D | Kconfig | 14 including NEON and GPU, Mali-450 graphics, several DDR3 options,
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| /arch/arm/mach-rockchip/rv1108/ |
| A D | Kconfig | 16 * 128M DDR3
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| /arch/x86/include/asm/arch-quark/ |
| A D | mrc.h | 46 DDR3, enumerator
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| /arch/arm/mach-rockchip/ |
| A D | Kconfig | 24 including NEON and GPU, Mali-400 graphics, several DDR3 options
39 including NEON and GPU, Mali-400 graphics, several DDR3 options
72 including NEON and GPU, Mali-400 graphics, several DDR3 options
123 including NEON and GPU, Mali-400 graphics, several DDR3 options
157 video interfaces supporting HDMI and eDP, several DDR3 options
225 video interfaces supporting HDMI and eDP, several DDR3 options
246 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
317 video interfaces supporting HDMI and eDP, several DDR3 options
401 two video interfaces supporting HDMI and eDP, several DDR3 options
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| /arch/arm/mach-rockchip/rk3399/ |
| A D | Kconfig | 61 * on-module DDR3 (1GB, 2GB and 4GB configurations available)
84 * 2GiB/4GiB DDR3 RAM
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| /arch/arm/mach-imx/ |
| A D | Kconfig | 170 bool "Enable DDRMC (DDR3) on-chip calibration"
173 Vybrid (vf610) SoC provides some on-chip facility to tune the DDR3
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| /arch/powerpc/dts/ |
| A D | turris1x.dts | 62 /* DDR3 SPD/EEPROM PSWP instruction */
76 /* DDR3 SPD/EEPROM */
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| /arch/arm/mach-rockchip/rk3288/ |
| A D | Kconfig | 107 2GB DDR3. Expansion connectors provide access to I2C, SPI, UART,
|