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Searched refs:RIFSC_RISC_SECCFGR0 (Results 1 – 1 of 1) sorted by relevance

/arch/arm/mach-stm32mp/stm32mp2/
A Drifsc.c17 #define RIFSC_RISC_SECCFGR0(id) (0x10 + 0x4 * (id)) macro
142 sec_reg_value = readl(base + RIFSC_RISC_SECCFGR0(reg_id)); in rifsc_check_access()

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