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Searched refs:SRC_BASE_ADDR (Results 1 – 20 of 20) sorted by relevance

/arch/arm/mach-imx/imx8m/
A Dpsci.c85 (void *)SRC_BASE_ADDR + SRC_GPR(cpu * 2)); in psci_cpu_on_write_entry_point()
88 (void *)SRC_BASE_ADDR + SRC_GPR(cpu * 2 + 1)); in psci_cpu_on_write_entry_point()
96 clrbits_le32((void *)SRC_BASE_ADDR + SRC_A53RCR1, A53_COREn_ENABLE(cpu)); in psci_cpu_on_power_on()
105 setbits_le32((void *)SRC_BASE_ADDR + SRC_A53RCR1, A53_COREn_ENABLE(cpu)); in psci_cpu_on_power_on()
/arch/arm/include/asm/arch-imx9/
A Dddr.h32 #define SRC_BASE_ADDR (0x44460000) macro
33 #define SRC_DPHY_BASE_ADDR (SRC_BASE_ADDR + 0x1400)
/arch/arm/mach-imx/
A Dinit.c91 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in init_src()
113 struct src *psrc = (struct src *)SRC_BASE_ADDR; in boot_mode_apply()
A Dimx_bootaux.c141 clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, in arch_auxiliary_core_up()
158 val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET); in arch_auxiliary_core_check_up()
A Dcpu.c37 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_imx_reset_cause()
478 if (((readl(SRC_BASE_ADDR + 0x58) & 0x00007FFF) >> 12) == 0x4) in get_boot_device()
/arch/arm/mach-imx/mx6/
A Dmp.c16 static struct src *src = (struct src *)SRC_BASE_ADDR;
A Dopos6ul.c63 struct src *psrc = (struct src *)SRC_BASE_ADDR; in board_late_init()
A Dsoc.c94 if (readl(SRC_BASE_ADDR + 0x1c) & (1 << 6)) in get_cpu_rev()
A Dddr.c1280 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in mx6_ddr3_cfg()
/arch/arm/mach-imx/mx7/
A Dpsci-mx7.c106 (SRC_BASE_ADDR + SRC_GPR1_MX7D + cpu * 8)
175 val = readl(SRC_BASE_ADDR + SRC_A7RCR1); in imx_enable_cpu_ca7()
177 writel(val, SRC_BASE_ADDR + SRC_A7RCR1); in imx_enable_cpu_ca7()
686 writel((u32)psci_system_resume, SRC_BASE_ADDR + SRC_GPR1_MX7D); in psci_system_suspend()
687 writel(val, SRC_BASE_ADDR + SRC_GPR2_MX7D); in psci_system_suspend()
A Dsoc.c450 struct src *psrc = (struct src *)SRC_BASE_ADDR; in boot_mode_getprisec()
A Dddr.c31 struct src *const src_regs = (struct src *)SRC_BASE_ADDR; in mx7_dram_cfg()
/arch/arm/mach-imx/mx7ulp/
A Dsoc.c314 u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28); in get_reset_cause()
315 u32 *reg_srs = (u32 *)(SRC_BASE_ADDR + 0x20); in get_reset_cause()
/arch/arm/cpu/armv7/vf610/
A Dgeneric.c290 struct src *src_regs = (struct src *)SRC_BASE_ADDR; in get_reset_cause()
/arch/arm/include/asm/arch-mx6/
A Dimx-regs.h200 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) macro
485 #define src_base ((struct src *)SRC_BASE_ADDR)
/arch/arm/include/asm/arch-mx5/
A Dimx-regs.h76 #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) macro
/arch/arm/include/asm/arch-mx7/
A Dimx-regs.h114 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x190000) macro
265 #define src_base ((struct src *)SRC_BASE_ADDR)
/arch/arm/include/asm/arch-imx8m/
A Dimx-regs.h32 #define SRC_BASE_ADDR 0x30390000 macro
/arch/arm/include/asm/arch-vf610/
A Dimx-regs.h85 #define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000) macro
/arch/arm/include/asm/arch-mx7ulp/
A Dimx-regs.h958 #define SRC_BASE_ADDR CMC1_RBASE macro

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