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/arch/arm/dts/
A Dsun50i-h6-gpu-opp.dtsi9 opp-hz = /bits/ 64 <216000000>;
14 opp-hz = /bits/ 64 <264000000>;
19 opp-hz = /bits/ 64 <312000000>;
24 opp-hz = /bits/ 64 <336000000>;
29 opp-hz = /bits/ 64 <360000000>;
34 opp-hz = /bits/ 64 <384000000>;
39 opp-hz = /bits/ 64 <408000000>;
44 opp-hz = /bits/ 64 <420000000>;
49 opp-hz = /bits/ 64 <432000000>;
54 opp-hz = /bits/ 64 <456000000>;
[all …]
A Dqemu-sbsa.dts42 reg = /bits/ 64 <SBSA_FLASH_BASE_ADDR
50 reg = /bits/ 64 <SBSA_UART_BASE_ADDR
57 reg = /bits/ 64 <0x60100000 0x00010000>;
63 reg = /bits/ 64 <0x60110000 0x00010000>;
72 reg = /bits/ 64 <0xf0000000 0x10000000>;
74 ranges = /bits/ 32 <0x01000000>,
75 /bits/ 64 <0
78 /bits/ 32 <0x02000000>,
79 /bits/ 64 <SBSA_PCIE_MMIO_BASE_ADDR
82 /bits/ 32 <0x43000000>,
[all …]
A Drk3229.dtsi18 opp-hz = /bits/ 64 <408000000>;
24 opp-hz = /bits/ 64 <600000000>;
28 opp-hz = /bits/ 64 <816000000>;
32 opp-hz = /bits/ 64 <1008000000>;
36 opp-hz = /bits/ 64 <1200000000>;
40 opp-hz = /bits/ 64 <1296000000>;
44 opp-hz = /bits/ 64 <1392000000>;
48 opp-hz = /bits/ 64 <1464000000>;
A Dsun50i-h5-cpu-opp.dtsi10 opp-hz = /bits/ 64 <408000000>;
16 opp-hz = /bits/ 64 <648000000>;
22 opp-hz = /bits/ 64 <816000000>;
28 opp-hz = /bits/ 64 <912000000>;
34 opp-hz = /bits/ 64 <960000000>;
40 opp-hz = /bits/ 64 <1008000000>;
46 opp-hz = /bits/ 64 <1056000000>;
52 opp-hz = /bits/ 64 <1104000000>;
58 opp-hz = /bits/ 64 <1152000000>;
A Dimx7d-pico-hobbit.dts69 ti,x-min = /bits/ 16 <0>;
70 ti,x-max = /bits/ 16 <4095>;
71 ti,y-min = /bits/ 16 <0>;
72 ti,y-max = /bits/ 16 <4095>;
73 ti,pressure-max = /bits/ 16 <1024>;
74 ti,x-plate-ohms = /bits/ 16 <90>;
75 ti,y-plate-ohms = /bits/ 16 <90>;
76 ti,debounce-max = /bits/ 16 <70>;
77 ti,debounce-tol = /bits/ 16 <3>;
78 ti,debounce-rep = /bits/ 16 <2>;
[all …]
A Dsun50i-a64-cpu-opp.dtsi12 opp-hz = /bits/ 64 <648000000>;
18 opp-hz = /bits/ 64 <816000000>;
24 opp-hz = /bits/ 64 <912000000>;
30 opp-hz = /bits/ 64 <960000000>;
36 opp-hz = /bits/ 64 <1008000000>;
42 opp-hz = /bits/ 64 <1056000000>;
48 opp-hz = /bits/ 64 <1104000000>;
54 opp-hz = /bits/ 64 <1152000000>;
A Dsun50i-h6-cpu-opp.dtsi13 opp-hz = /bits/ 64 <480000000>;
22 opp-hz = /bits/ 64 <720000000>;
31 opp-hz = /bits/ 64 <816000000>;
40 opp-hz = /bits/ 64 <888000000>;
49 opp-hz = /bits/ 64 <1080000000>;
58 opp-hz = /bits/ 64 <1320000000>;
67 opp-hz = /bits/ 64 <1488000000>;
76 opp-hz = /bits/ 64 <1608000000>;
85 opp-hz = /bits/ 64 <1704000000>;
94 opp-hz = /bits/ 64 <1800000000>;
A Dzynqmp-binman.dts41 load = /bits/ 64 <CONFIG_TEXT_BASE>;
42 entry = /bits/ 64 <CONFIG_TEXT_BASE>;
55 load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
56 entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
70 load = /bits/ 64 <CONFIG_BL32_LOAD_ADDR>;
71 entry = /bits/ 64 <CONFIG_BL32_LOAD_ADDR>;
126 load = /bits/ 64 <CONFIG_TEXT_BASE>;
127 entry = /bits/ 64 <CONFIG_TEXT_BASE>;
140 load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
141 entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
[all …]
A Dsun8i-r40-cpu-opp.dtsi7 opp-hz = /bits/ 64 <720000000>;
13 opp-hz = /bits/ 64 <912000000>;
19 opp-hz = /bits/ 64 <1008000000>;
25 opp-hz = /bits/ 64 <1104000000>;
31 opp-hz = /bits/ 64 <1200000000>;
A Dat91sam9261ek.dts45 bits-per-pixel = <16>;
131 ti,x-min = /bits/ 16 <150>;
132 ti,x-max = /bits/ 16 <3830>;
133 ti,y-min = /bits/ 16 <190>;
134 ti,y-max = /bits/ 16 <3830>;
136 ti,x-plate-ohms = /bits/ 16 <450>;
137 ti,y-plate-ohms = /bits/ 16 <250>;
138 ti,pressure-max = /bits/ 16 <15000>;
139 ti,debounce-rep = /bits/ 16 <0>;
140 ti,debounce-tol = /bits/ 16 <65535>;
[all …]
A Dzynqmp-zc1232-revA.dts72 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
73 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
74 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
75 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
76 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
77 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
78 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
79 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
A Dtegra124-xiaomi-mocha.dts312 dev-ctrl = /bits/ 8 <0x83>;
313 init-brt = /bits/ 8 <0x1f>;
320 rom-val = /bits/ 8 <0x80>;
325 rom-val = /bits/ 8 <0x21>;
330 rom-val = /bits/ 8 <0xff>;
335 rom-val = /bits/ 8 <0x3f>;
340 rom-val = /bits/ 8 <0x20>;
345 rom-val = /bits/ 8 <0x00>;
350 rom-val = /bits/ 8 <0x72>;
355 rom-val = /bits/ 8 <0x24>;
[all …]
A Dnuvoton-npcm750-evb.dts295 fan-tach-ch = /bits/ 8 <0x00 0x01>;
300 fan-tach-ch = /bits/ 8 <0x02 0x03>;
301 cooling-levels = /bits/ 8 <127 255>;
305 fan-tach-ch = /bits/ 8 <0x04 0x05>;
306 cooling-levels = /bits/ 8 <127 255>;
310 fan-tach-ch = /bits/ 8 <0x06 0x07>;
311 cooling-levels = /bits/ 8 <127 255>;
315 fan-tach-ch = /bits/ 8 <0x08 0x09>;
320 fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
325 fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
[all …]
A Dda850.dtsi124 pinctrl-single,bits = <
130 pinctrl-single,bits = <
136 pinctrl-single,bits = <
142 pinctrl-single,bits = <
148 pinctrl-single,bits = <
154 pinctrl-single,bits = <
160 pinctrl-single,bits = <
166 pinctrl-single,bits = <
172 pinctrl-single,bits = <
181 pinctrl-single,bits = <
[all …]
A Dsun8i-a33.dtsi54 opp-hz = /bits/ 64 <120000000>;
60 opp-hz = /bits/ 64 <240000000>;
66 opp-hz = /bits/ 64 <312000000>;
72 opp-hz = /bits/ 64 <408000000>;
78 opp-hz = /bits/ 64 <480000000>;
84 opp-hz = /bits/ 64 <504000000>;
90 opp-hz = /bits/ 64 <600000000>;
96 opp-hz = /bits/ 64 <648000000>;
102 opp-hz = /bits/ 64 <720000000>;
108 opp-hz = /bits/ 64 <816000000>;
[all …]
A Duniphier-ld20.dtsi101 opp-hz = /bits/ 64 <250000000>;
649 bits = <4 2>;
653 bits = <4 2>;
657 bits = <4 2>;
661 bits = <4 2>;
665 bits = <0 4>;
669 bits = <0 4>;
673 bits = <0 4>;
677 bits = <0 4>;
681 bits = <0 4>;
[all …]
/arch/arm/mach-imx/mx7/
A Dddr.c155 bits++; in imx_ddr_size()
158 bits++; in imx_ddr_size()
161 bits++; in imx_ddr_size()
164 bits++; in imx_ddr_size()
168 bits++; in imx_ddr_size()
171 bits++; in imx_ddr_size()
174 bits++; in imx_ddr_size()
177 bits++; in imx_ddr_size()
181 bits++; in imx_ddr_size()
184 bits++; in imx_ddr_size()
[all …]
/arch/arm/mach-imx/
A Dmmdc_size.c44 int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */ in imx_ddr_size() local
46 bits += ESD_MMDC_CTL_GET_ROW(ctl); in imx_ddr_size()
47 bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)]; in imx_ddr_size()
48 bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)]; in imx_ddr_size()
49 bits += ESD_MMDC_CTL_GET_WIDTH(ctl); in imx_ddr_size()
50 bits += ESD_MMDC_CTL_GET_CS1(ctl); in imx_ddr_size()
53 if (bits == 32) in imx_ddr_size()
56 return 1 << bits; in imx_ddr_size()
/arch/arm/mach-sunxi/
A Dpmic_bus.c86 int pmic_bus_setbits(u8 reg, u8 bits) in pmic_bus_setbits() argument
95 if ((val & bits) == bits) in pmic_bus_setbits()
98 val |= bits; in pmic_bus_setbits()
102 int pmic_bus_clrbits(u8 reg, u8 bits) in pmic_bus_clrbits() argument
111 if (!(val & bits)) in pmic_bus_clrbits()
114 val &= ~bits; in pmic_bus_clrbits()
/arch/mips/mach-octeon/
A Dcvmx-helper-jtag.c77 uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data) in cvmx_helper_qlm_jtag_shift() argument
89 jtgd.s.shft_cnt = bits - 1; in cvmx_helper_qlm_jtag_shift()
96 return jtgd.s.shft_reg >> (32 - bits); in cvmx_helper_qlm_jtag_shift()
109 void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits) in cvmx_helper_qlm_jtag_shift_zeros() argument
111 while (bits > 0) { in cvmx_helper_qlm_jtag_shift_zeros()
112 int n = bits; in cvmx_helper_qlm_jtag_shift_zeros()
117 bits -= n; in cvmx_helper_qlm_jtag_shift_zeros()
/arch/riscv/dts/
A Dbinman.dtsi36 load = /bits/ 64 <CONFIG_TEXT_BASE>;
48 load = /bits/ 64 <CONFIG_TEXT_BASE>;
62 load = /bits/ 64 <CONFIG_SPL_OPTEE_LOAD_ADDR>;
75 load = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
76 entry = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
/arch/x86/cpu/tangier/
A Dpinmux.c95 static int mrfld_pinconfig_protected(unsigned int pin, u32 mask, u32 bits) in mrfld_pinconfig_protected() argument
115 v = (value & ~mask) | (bits & mask); in mrfld_pinconfig_protected()
118 v, (u32)bufcfg, bits, mask, bufcfg); in mrfld_pinconfig_protected()
123 static int mrfld_pinconfig(unsigned int pin, u32 mask, u32 bits) in mrfld_pinconfig() argument
142 v = (value & ~mask) | (bits & mask); in mrfld_pinconfig()
146 v, (u32)bufcfg, bits, mask, bufcfg); in mrfld_pinconfig()
/arch/arm/include/asm/arch-sunxi/
A Dpmic_bus.h16 int pmic_bus_setbits(u8 reg, u8 bits);
17 int pmic_bus_clrbits(u8 reg, u8 bits);
/arch/mips/mach-octeon/include/mach/
A Dcvmx-helper-jtag.h54 u32 cvmx_helper_qlm_jtag_shift(int qlm, int bits, u32 data);
66 void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits);
/arch/arm/cpu/armv7/
A Dnonsec_virt.S33 and \tmp, \tmp, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
75 bic r5, r5, #0x4a @ clear IRQ, EA, nET bits
76 orr r5, r5, #0x31 @ enable NS, AW, FW bits
94 ands r4, r4, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits
119 bfc \addr, #0, #15 @ clear reserved bits
170 mvn r1, #0 @ all bits to 1
176 str r1, [r3, #GICC_CTLR] @ and clear all other bits
194 and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits

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