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Searched refs:bridge (Results 1 – 25 of 46) sorted by relevance

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/arch/powerpc/cpu/mpc83xx/
A Dpcie.c86 out_le32(&pex->bridge.pex_csb_ctrl, in mpc83xx_pcie_init_bus()
87 in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE | in mpc83xx_pcie_init_bus()
91 out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE | in mpc83xx_pcie_init_bus()
95 out_win = &pex->bridge.pex_outbound_win[0]; in mpc83xx_pcie_init_bus()
108 out_win = &pex->bridge.pex_outbound_win[i + 1]; in mpc83xx_pcie_init_bus()
120 out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE); in mpc83xx_pcie_init_bus()
127 in_win = &pex->bridge.pex_inbound_win[i]; in mpc83xx_pcie_init_bus()
153 in_win = &pex->bridge.pex_inbound_win[i]; in mpc83xx_pcie_init_bus()
161 out_le32(&pex->bridge.pex_int_axi_misc_enb, in mpc83xx_pcie_init_bus()
162 in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0); in mpc83xx_pcie_init_bus()
A DKconfig198 the host bridge.
/arch/arm/include/asm/arch-imx8ulp/
A Dsys_proto.h12 int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm);
13 int xrdc_config_pdac_openacc(u32 bridge, u32 index);
A Drdc.h19 int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm);
20 int xrdc_config_pdac_openacc(u32 bridge, u32 index);
/arch/arm/dts/
A Dsocfpga_arria10-handoff.dtsi256 compatible = "altr,socfpga-hps2fpga-bridge";
262 compatible = "altr,socfpga-lwhps2fpga-bridge";
268 compatible = "altr,socfpga-fpga2hps-bridge";
274 compatible = "altr,socfpga-fpga2sdram0-bridge";
280 compatible = "altr,socfpga-fpga2sdram1-bridge";
286 compatible = "altr,socfpga-fpga2sdram2-bridge";
A Dsocfpga_stratix10_socdk-u-boot.dtsi18 compatible = "altr,freeze-bridge-controller";
A Dimx6q-b850v3.dts224 bridge@1,0 {
232 bridge@2,1 {
247 bridge@2,2 {
A Dsun8i-a83t-cubietruck-plus.dts172 /* GL830 USB-to-SATA bridge here */
384 regulator-name = "dp-bridge-1";
390 regulator-name = "dp-bridge-2";
A Dsun6i-a31s-primo81.dts244 regulator-name = "vdd-mipi-bridge";
249 vdd-mipi-bridge-supply = <&reg_eldo3>;
A Dtegra30-lg-p880.dts105 bridge-spi@2 {
A Dtegra30-lg-p895.dts112 bridge-spi@2 {
A Dtegra20-samsung-n1.dts79 cmc623: bridge@38 {
A Duniphier-ld4.dtsi266 reset-names = "host", "bridge";
285 reset-names = "host", "bridge", "hw";
A Duniphier-sld8.dtsi270 reset-names = "host", "bridge";
290 reset-names = "host", "bridge", "hw";
A Dimx8mm-mx8menlo.dts192 /delete-node/ bridge@2c;
A Duniphier-pro4.dtsi301 reset-names = "host", "bridge";
321 reset-names = "host", "bridge", "hw";
339 reset-names = "host", "bridge";
A Dsun8i-a83t-bananapi-m3.dts110 * Power supply for the SATA disk, behind a USB-SATA bridge.
141 /* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */
A Dtegra20-lg-star.dts449 bridge: cpu-bridge { label
A Dsocfpga_agilex5_socdk-u-boot.dtsi19 compatible = "altr,freeze-bridge-controller";
A Dimx6qdl-udoo.dtsi44 * but with LVDS bridge chip attached,
/arch/arm/mach-imx/imx8ulp/
A Drdc.c132 int xrdc_config_pdac_openacc(u32 bridge, u32 index) in xrdc_config_pdac_openacc() argument
137 switch (bridge) { in xrdc_config_pdac_openacc()
158 int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm) in xrdc_config_pdac() argument
163 switch (bridge) { in xrdc_config_pdac()
/arch/x86/dts/
A Dcrownbay.dts82 compatible = "pci-bridge";
89 compatible = "pci-bridge";
/arch/arm/mach-socfpga/
A Dmisc.c224 U_BOOT_CMD(bridge, 3, 1, do_bridge,
/arch/arm/mach-rockchip/px30/
A DKconfig58 - USB<->CAN bridge controller (STM32 only)
/arch/nios2/dts/
A D3c120_devboard.dts60 pb_cpu_to_io: bridge@0x8000000 {

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