Searched refs:div1 (Results 1 – 10 of 10) sorted by relevance
| /arch/sh/lib/ |
| A D | udivsi3.S | 15 div1 r5,r4
17 div1 r5,r4; div1 r5,r4; div1 r5,r4
18 div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
21 div1 r5,r4; rotcl r0
22 div1 r5,r4; rotcl r0
23 div1 r5,r4; rotcl r0
24 rts; div1 r5,r4
37 div1 r5,r4
43 div1 r5,r4
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| A D | udivsi3_i4i-Os.S | 38 div1 r5,r4
40 div1 r5,r4
41 div1 r5,r4
43 div1 r5,r4
48 div1 r5,r4
50 div1 r5,r4
58 div1 r5,r4
60 div1 r5,r4; div1 r5,r4; div1 r5,r4
61 div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
65 div1 r5,r4
[all …]
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| A D | udivsi3_i4i.S | 54 div1 r5,r0
56 div1 r5,r0
57 div1 r5,r0
59 div1 r5,r0
101 div1 r5,r0
108 div1 r5,r0
111 div1 r5,r0
114 div1 r5,r0
117 div1 r5,r0
119 div1 r5,r0
[all …]
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| A D | udiv_qrnnd.S | 28 div1 r6,r0
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| /arch/arm/mach-sunxi/ |
| A D | clock_sun8i_a83t.c | 110 unsigned int div1 = 0, div2 = 0; in clock_set_pll5() local
116 div1 << CCM_PLL5_DIV1_SHIFT, &ccm->pll5_cfg); in clock_set_pll5()
128 int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> in clock_get_pll6() local
132 return 24000000 * n / div1 / div2; in clock_get_pll6()
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| A D | clock_sun50i_h6.c | 243 int div1, m; in clock_get_pll6() local
246 div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >> in clock_get_pll6()
249 div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> in clock_get_pll6()
263 return 24000000U * n / m / div1 / div2; in clock_get_pll6()
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| /arch/arm/mach-s5pc1xx/include/mach/ |
| A D | clock.h | 29 unsigned int div1; member
65 unsigned int div1; member
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| /arch/arm/include/asm/arch-sunxi/ |
| A D | clock_sun50i_h6.h | 64 #define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0) argument
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| /arch/arm/mach-keystone/include/mach/ |
| A D | clock_defs.h | 24 u32 div1; /* 18 */ member
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| /arch/arm/mach-keystone/ |
| A D | clock.c | 130 offset = pllctl_reg(data->pll, div1) + i; in configure_main_pll()
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