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Searched refs:divider (Results 1 – 25 of 38) sorted by relevance

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/arch/x86/lib/
A Ddiv64.c57 static u64 _64bit_divide(u64 dividend, u64 divider, u64 *rem_p) in _64bit_divide() argument
65 if (!divider) in _64bit_divide()
66 return 1 / (u32)divider; in _64bit_divide()
70 if (divider > MAX_32BIT_UINT) { in _64bit_divide()
73 *rem_p = divider; in _64bit_divide()
75 result = (u32)dividend / (u32)divider; in _64bit_divide()
77 *rem_p = (u32)dividend % (u32)divider; in _64bit_divide()
82 while (divider <= dividend) { in _64bit_divide()
83 u64 locald = divider; in _64bit_divide()
/arch/arm/mach-tegra/
A Dclock.c257 u64 divider = parent_rate * 2; in clk_get_divider() local
260 divider += rate - 1; in clk_get_divider()
261 do_div(divider, rate); in clk_get_divider()
263 if ((s64)divider - 2 < 0) in clk_get_divider()
269 return divider - 2; in clk_get_divider()
309 int divider) in get_rate_from_divider() argument
314 do_div(rate, divider + 2); in get_rate_from_divider()
397 divider); in find_best_divider()
404 best_divider = divider; in find_best_divider()
461 int divider; in clock_adjust_periph_pll_div() local
[all …]
/arch/powerpc/cpu/mpc8xx/
A Dspeed.c23 uint divider = 1 << (((sccr & SCCR_DFBRG11) >> 11) * 2); in get_clocks() local
41 gd->arch.brg_clk = gd->cpu_clk / divider; in get_clocks()
/arch/arm/dts/
A Ddra7xx-clocks.dtsi211 compatible = "ti,divider-clock";
222 compatible = "ti,divider-clock";
231 compatible = "ti,divider-clock";
242 compatible = "ti,divider-clock";
274 compatible = "ti,divider-clock";
300 compatible = "ti,divider-clock";
344 compatible = "ti,divider-clock";
382 compatible = "ti,divider-clock";
420 compatible = "ti,divider-clock";
433 compatible = "ti,divider-clock";
[all …]
A Dimx53-usbarmory.dts153 lltc,fb-voltage-divider = <100000 158000>;
162 lltc,fb-voltage-divider = <180000 191000>;
171 lltc,fb-voltage-divider = <270000 100000>;
180 lltc,fb-voltage-divider = <511000 158000>;
188 lltc,fb-voltage-divider = <100000 158000>;
196 lltc,fb-voltage-divider = <180000 191000>;
A Dimx6qdl-gw5913.dtsi167 gw,voltage-divider-ohms = <22100 1000>;
175 gw,voltage-divider-ohms = <22100 10000>;
182 gw,voltage-divider-ohms = <10000 10000>;
189 gw,voltage-divider-ohms = <10000 10000>;
226 gw,voltage-divider-ohms = <10000 10000>;
233 gw,voltage-divider-ohms = <10000 10000>;
A Dam43xx-clocks.dtsi210 compatible = "ti,divider-clock";
221 compatible = "ti,divider-clock";
232 compatible = "ti,divider-clock";
250 compatible = "ti,divider-clock";
268 compatible = "ti,divider-clock";
286 compatible = "ti,divider-clock";
305 compatible = "ti,divider-clock";
565 compatible = "ti,divider-clock";
588 compatible = "ti,divider-clock";
664 compatible = "ti,divider-clock";
[all …]
A Dqcs404-evb-4000-u-boot.dtsi24 /* This defines the bit clock divider which defines the baud rate.
25 * 0xFF is a divider of 16 for both the RX and TX lines. The QCS404
A Dimx6qdl-dhcom.dtsi138 lltc,fb-voltage-divider = <100000 110000>;
148 lltc,fb-voltage-divider = <100000 28000>;
157 lltc,fb-voltage-divider = <100000 110000>;
167 lltc,fb-voltage-divider = <100000 93100>;
176 lltc,fb-voltage-divider = <102000 29400>;
184 lltc,fb-voltage-divider = <100000 41200>;
A Dimx6qdl-gw552x.dtsi289 lltc,fb-voltage-divider = <127000 200000>;
300 lltc,fb-voltage-divider = <301000 200000>;
311 lltc,fb-voltage-divider = <127000 200000>;
322 lltc,fb-voltage-divider = <221000 200000>;
333 lltc,fb-voltage-divider = <487000 200000>;
343 lltc,fb-voltage-divider = <634000 200000>;
A Dimx6qdl-gw5910.dtsi191 gw,voltage-divider-ohms = <22100 1000>;
199 gw,voltage-divider-ohms = <22100 10000>;
206 gw,voltage-divider-ohms = <10000 10000>;
213 gw,voltage-divider-ohms = <10000 10000>;
250 gw,voltage-divider-ohms = <10000 10000>;
257 gw,voltage-divider-ohms = <10000 10000>;
264 gw,voltage-divider-ohms = <10000 10000>;
A Dam33xx-clocks.dtsi178 compatible = "ti,divider-clock";
187 compatible = "ti,divider-clock";
196 compatible = "ti,divider-clock";
212 compatible = "ti,divider-clock";
228 compatible = "ti,divider-clock";
252 compatible = "ti,divider-clock";
269 compatible = "ti,divider-clock";
507 compatible = "ti,divider-clock";
522 compatible = "ti,divider-clock";
A Domap3xxx-clocks.dtsi23 compatible = "ti,divider-clock";
202 compatible = "ti,divider-clock";
243 compatible = "ti,divider-clock";
290 compatible = "ti,divider-clock";
308 compatible = "ti,divider-clock";
333 compatible = "ti,divider-clock";
358 compatible = "ti,divider-clock";
417 compatible = "ti,divider-clock";
445 compatible = "ti,divider-clock";
473 compatible = "ti,divider-clock";
[all …]
A Dimx6qdl-gw51xx.dtsi299 lltc,fb-voltage-divider = <127000 200000>;
310 lltc,fb-voltage-divider = <301000 200000>;
321 lltc,fb-voltage-divider = <127000 200000>;
332 lltc,fb-voltage-divider = <221000 200000>;
343 lltc,fb-voltage-divider = <487000 200000>;
353 lltc,fb-voltage-divider = <634000 200000>;
A Dimx6qdl-gw52xx.dtsi368 lltc,fb-voltage-divider = <127000 200000>;
379 lltc,fb-voltage-divider = <301000 200000>;
390 lltc,fb-voltage-divider = <127000 200000>;
401 lltc,fb-voltage-divider = <221000 200000>;
412 lltc,fb-voltage-divider = <487000 200000>;
430 lltc,fb-voltage-divider = <634000 200000>;
A Dimx6qdl-gw53xx.dtsi365 lltc,fb-voltage-divider = <127000 200000>;
376 lltc,fb-voltage-divider = <301000 200000>;
387 lltc,fb-voltage-divider = <127000 200000>;
398 lltc,fb-voltage-divider = <221000 200000>;
409 lltc,fb-voltage-divider = <487000 200000>;
427 lltc,fb-voltage-divider = <634000 200000>;
A Dimx6qdl-gw551x.dtsi358 lltc,fb-voltage-divider = <127000 200000>;
369 lltc,fb-voltage-divider = <221000 200000>;
380 lltc,fb-voltage-divider = <127000 200000>;
391 lltc,fb-voltage-divider = <200000 56200>;
402 lltc,fb-voltage-divider = <301000 200000>;
420 lltc,fb-voltage-divider = <634000 200000>;
A Dimx6qdl-gw553x.dtsi346 lltc,fb-voltage-divider = <127000 200000>;
357 lltc,fb-voltage-divider = <221000 200000>;
368 lltc,fb-voltage-divider = <127000 200000>;
379 lltc,fb-voltage-divider = <200000 56200>;
390 lltc,fb-voltage-divider = <301000 200000>;
408 lltc,fb-voltage-divider = <634000 200000>;
A Dimx6qdl-dhcom-som.dtsi253 lltc,fb-voltage-divider = <100000 110000>;
263 lltc,fb-voltage-divider = <100000 28000>;
272 lltc,fb-voltage-divider = <100000 110000>;
282 lltc,fb-voltage-divider = <100000 93100>;
291 lltc,fb-voltage-divider = <102000 29400>;
299 lltc,fb-voltage-divider = <100000 41200>;
A Dimx6qdl-gw5903.dtsi378 lltc,fb-voltage-divider = <301000 200000>;
389 lltc,fb-voltage-divider = <221000 200000>;
400 lltc,fb-voltage-divider = <127000 200000>;
412 lltc,fb-voltage-divider = <127000 200000>;
424 lltc,fb-voltage-divider = <100000 261000>;
434 lltc,fb-voltage-divider = <634000 200000>;
A Dimx6qdl-gw5904.dtsi443 lltc,fb-voltage-divider = <127000 200000>;
454 lltc,fb-voltage-divider = <301000 200000>;
465 lltc,fb-voltage-divider = <127000 200000>;
476 lltc,fb-voltage-divider = <221000 200000>;
487 lltc,fb-voltage-divider = <487000 200000>;
497 lltc,fb-voltage-divider = <634000 200000>;
/arch/m68k/cpu/mcf532x/
A Dspeed.c55 int divider; in get_sys_clock() local
59 divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF); in get_sys_clock()
61 return (FREF / (3 * (1 << divider))); in get_sys_clock()
64 return (FREF / (2 << divider)); in get_sys_clock()
/arch/arm/cpu/arm926ejs/mxs/
A Dspl_mem_init.c148 const unsigned char divider = 33; in mxs_mem_init_clock() local
151 const unsigned char divider = 21; in mxs_mem_init_clock() local
161 writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK), in mxs_mem_init_clock()
/arch/arm/cpu/armv8/fsl-layerscape/
A DKconfig541 int "Platform clock divider"
548 This is the divider that is used to derive Platform clock from
553 int "DSPI clock divider"
561 int "DUART clock divider"
571 int "I2C clock divider"
580 This is the divider that is used to derive I2C clock from Platform
584 int "IFC clock divider"
593 This is the divider that is used to derive IFC clock from Platform
597 int "LPUART clock divider"
605 int "SDHC clock divider"
[all …]
/arch/arm/mach-sc5xx/
A DKconfig286 CCLK_DIV controls the core clock divider
294 SCLK_DIV controls the system clock divider
317 DCLK_DIV controls the DDR clock divider
325 OCLK_DIV controls the output clock divider
369 PLL divider value for the 3rd PLL.
390 CCLK_DIV controls the core clock divider
398 SCLK_DIV controls the system clock divider
422 DCLK_DIV controls the DDR clock divider
430 OCLK_DIV controls the output clock divider

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