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Searched refs:io (Results 1 – 25 of 172) sorted by relevance

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/arch/sandbox/cpu/
A Dstate.c114 debug(" - read %s\n", io->name); in sandbox_read_state_nodes()
115 if (!io->read) in sandbox_read_state_nodes()
125 ret = io->read(blob, node); in sandbox_read_state_nodes()
139 ret = io->read(NULL, -1); in sandbox_read_state_nodes()
142 io->name); in sandbox_read_state_nodes()
152 struct sandbox_state_io *io; in sandbox_read_state() local
169 for (; io < ll_entry_end(struct sandbox_state_io, state_io); io++) { in sandbox_read_state()
204 if (!io->write) in sandbox_write_state_node()
234 ret = io->write(blob, node); in sandbox_write_state_node()
245 struct sandbox_state_io *io; in sandbox_write_state() local
[all …]
/arch/arm/dts/
A Dzynqmp-sc-vm-p-m1369-00-revA.dtso153 #io-channel-cells = <1>;
160 #io-channel-cells = <1>;
167 #io-channel-cells = <1>;
174 #io-channel-cells = <1>;
181 #io-channel-cells = <1>;
188 #io-channel-cells = <1>;
195 #io-channel-cells = <1>;
202 #io-channel-cells = <1>;
209 #io-channel-cells = <1>;
216 #io-channel-cells = <1>;
[all …]
A Dzynqmp-sc-vn-p-b2197-00-revA.dtso232 #io-channel-cells = <1>;
239 #io-channel-cells = <1>;
246 #io-channel-cells = <1>;
253 #io-channel-cells = <1>;
260 #io-channel-cells = <1>;
267 #io-channel-cells = <1>;
274 #io-channel-cells = <1>;
281 #io-channel-cells = <1>;
288 #io-channel-cells = <1>;
295 #io-channel-cells = <1>;
[all …]
A Dzynqmp-e-a2197-00-revA.dts262 #io-channel-cells = <1>;
270 #io-channel-cells = <1>;
278 #io-channel-cells = <1>;
286 #io-channel-cells = <1>;
294 #io-channel-cells = <1>;
302 #io-channel-cells = <1>;
322 #io-channel-cells = <1>;
330 #io-channel-cells = <1>;
338 #io-channel-cells = <1>;
346 #io-channel-cells = <1>;
[all …]
A Dzynqmp-zcu670-revA.dts74 ina226-vccint-io-bram {
270 #io-channel-cells = <1>;
277 #io-channel-cells = <1>;
284 #io-channel-cells = <1>;
291 #io-channel-cells = <1>;
298 #io-channel-cells = <1>;
305 #io-channel-cells = <1>;
312 #io-channel-cells = <1>;
319 #io-channel-cells = <1>;
326 #io-channel-cells = <1>;
[all …]
A Dzynqmp-zcu670-revB.dts74 ina226-vccint-io-bram {
270 #io-channel-cells = <1>;
277 #io-channel-cells = <1>;
284 #io-channel-cells = <1>;
291 #io-channel-cells = <1>;
298 #io-channel-cells = <1>;
305 #io-channel-cells = <1>;
312 #io-channel-cells = <1>;
319 #io-channel-cells = <1>;
326 #io-channel-cells = <1>;
[all …]
A Dzynqmp-zcu208-revA.dts71 ina226-vccint-io-bram {
261 #io-channel-cells = <1>;
268 #io-channel-cells = <1>;
275 #io-channel-cells = <1>;
282 #io-channel-cells = <1>;
289 #io-channel-cells = <1>;
296 #io-channel-cells = <1>;
303 #io-channel-cells = <1>;
310 #io-channel-cells = <1>;
317 #io-channel-cells = <1>;
[all …]
A Dzynqmp-zcu216-revA.dts71 ina226-vccint-io-bram {
271 #io-channel-cells = <1>;
278 #io-channel-cells = <1>;
285 #io-channel-cells = <1>;
292 #io-channel-cells = <1>;
299 #io-channel-cells = <1>;
306 #io-channel-cells = <1>;
313 #io-channel-cells = <1>;
320 #io-channel-cells = <1>;
327 #io-channel-cells = <1>;
[all …]
A Dzynqmp-zcu106-revA.dts307 #io-channel-cells = <1>;
314 #io-channel-cells = <1>;
321 #io-channel-cells = <1>;
328 #io-channel-cells = <1>;
335 #io-channel-cells = <1>;
342 #io-channel-cells = <1>;
349 #io-channel-cells = <1>;
356 #io-channel-cells = <1>;
363 #io-channel-cells = <1>;
370 #io-channel-cells = <1>;
[all …]
A Dzynqmp-zcu102-revA.dts296 #io-channel-cells = <1>;
303 #io-channel-cells = <1>;
310 #io-channel-cells = <1>;
317 #io-channel-cells = <1>;
324 #io-channel-cells = <1>;
331 #io-channel-cells = <1>;
338 #io-channel-cells = <1>;
345 #io-channel-cells = <1>;
352 #io-channel-cells = <1>;
359 #io-channel-cells = <1>;
[all …]
A Dzynqmp-zcu111-revA.dts247 #io-channel-cells = <1>;
254 #io-channel-cells = <1>;
261 #io-channel-cells = <1>;
268 #io-channel-cells = <1>;
275 #io-channel-cells = <1>;
282 #io-channel-cells = <1>;
289 #io-channel-cells = <1>;
296 #io-channel-cells = <1>;
303 #io-channel-cells = <1>;
310 #io-channel-cells = <1>;
[all …]
A Dzynqmp-g-a2197-00-revA.dts43 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
47 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
51 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
55 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
59 io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>;
229 #io-channel-cells = <1>;
236 #io-channel-cells = <1>;
243 #io-channel-cells = <1>;
250 #io-channel-cells = <1>;
257 #io-channel-cells = <1>;
[all …]
A Dste-ab8505.dtsi12 io-channels = <&gpadc 0x02>, /* Battery temperature */
54 #io-channel-cells = <1>;
114 io-channels = <&gpadc 0x08>;
115 io-channel-names = "main_bat_v";
132 io-channels = <&gpadc 0x02>,
134 io-channel-names = "btemp_ball",
171 io-channels = <&gpadc 0x09>,
173 io-channel-names = "vbus_v",
A Dste-ab8500.dtsi12 io-channels = <&gpadc 0x02>, /* Battery temperature */
58 #io-channel-cells = <1>;
127 io-channels = <&gpadc 0x06>,
129 io-channel-names = "aux1", "aux2";
150 io-channels = <&gpadc 0x08>;
151 io-channel-names = "main_bat_v";
167 io-channels = <&gpadc 0x02>,
169 io-channel-names = "btemp_ball",
205 io-channels = <&gpadc 0x03>,
209 io-channel-names = "main_charger_v",
A Dzynqmp-m-a2197-01-revA.dts48 io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
52 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
56 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
60 io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
68 io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;
213 #io-channel-cells = <1>;
220 #io-channel-cells = <1>;
227 #io-channel-cells = <1>;
234 #io-channel-cells = <1>;
241 #io-channel-cells = <1>;
[all …]
A Dzynqmp-m-a2197-02-revA.dts48 io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
52 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
56 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
60 io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
64 io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;
208 #io-channel-cells = <1>;
215 #io-channel-cells = <1>;
222 #io-channel-cells = <1>;
229 #io-channel-cells = <1>;
236 #io-channel-cells = <1>;
A Dzynqmp-m-a2197-03-revA.dts48 io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
52 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
56 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
60 io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
64 io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;
212 #io-channel-cells = <1>;
219 #io-channel-cells = <1>;
226 #io-channel-cells = <1>;
233 #io-channel-cells = <1>;
240 #io-channel-cells = <1>;
A Dr9a06g032.dtsi178 reg-io-width = <4>;
189 reg-io-width = <4>;
200 reg-io-width = <4>;
211 reg-io-width = <4>;
224 reg-io-width = <4>;
237 reg-io-width = <4>;
250 reg-io-width = <4>;
263 reg-io-width = <4>;
442 reg-io-width = <4>;
452 reg-io-width = <4>;
/arch/mips/mach-octeon/include/mach/
A Dcvmx-pcie.h33 u64 io : 1; /* 1 for IO space access */ member
50 u64 io : 1; /* 1 for IO space access */ member
58 } io; member
62 u64 io : 1; /* 1 for IO space access */ member
/arch/arm/cpu/arm926ejs/mxs/
A Dclock.c144 void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq) in mxs_set_ioclk() argument
154 if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1)) in mxs_set_ioclk()
165 io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */ in mxs_set_ioclk()
177 static uint32_t mxs_get_ioclk(enum mxs_ioclock io) in mxs_get_ioclk() argument
184 if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1)) in mxs_get_ioclk()
187 io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */ in mxs_get_ioclk()
/arch/x86/include/asm/arch-quark/
A Dmsg_port.h130 msg_port_generic_clrsetbits(io, port, reg, clr, 0)
132 msg_port_generic_clrsetbits(io, port, reg, 0, set)
134 msg_port_generic_clrsetbits(io, port, reg, clr, set)
/arch/riscv/dts/
A Dk230.dtsi106 reg-io-width = <4>;
116 reg-io-width = <4>;
126 reg-io-width = <4>;
136 reg-io-width = <4>;
146 reg-io-width = <4>;
A Dcv18xx.dtsi151 reg-io-width = <4>;
162 reg-io-width = <4>;
173 reg-io-width = <4>;
184 reg-io-width = <4>;
195 reg-io-width = <4>;
A Dk1.dtsi335 reg-io-width = <4>;
345 reg-io-width = <4>;
355 reg-io-width = <4>;
365 reg-io-width = <4>;
375 reg-io-width = <4>;
385 reg-io-width = <4>;
395 reg-io-width = <4>;
405 reg-io-width = <4>;
415 reg-io-width = <4>;
455 reg-io-width = <4>;
/arch/arm/include/asm/arch-tegra/
A Dpinmux.h116 u32 io:2; /* input or output PMUX_PIN_... */ member
162 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);

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