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/arch/powerpc/cpu/mpc85xx/
A Dspl_minimal.c17 ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR; in cpu_init_f() local
19 out_be32(&l2cache->l2srbar0, CFG_SYS_INIT_L2_ADDR); in cpu_init_f()
22 out_be32(&l2cache->l2errdis, in cpu_init_f()
26 out_be32(&l2cache->l2ctl, in cpu_init_f()
A Dcpu_init.c457 struct ccsr_cluster_l2 __iomem *l2cache; in enable_cluster_l2() local
498 while ((in_be32(&l2cache->l2csr0) in enable_cluster_l2()
532 cache_ctl = l2cache->l2ctl; in l2cache_init()
537 out_be32(&l2cache->l2srbar0, 0x0); in l2cache_init()
538 out_be32(&l2cache->l2srbar1, 0x0); in l2cache_init()
541 clrbits_be32(&l2cache->l2errdis, in l2cache_init()
546 clrbits_be32(&l2cache->l2ctl, in l2cache_init()
589 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { in l2cache_init()
592 u32 l2srbar = l2cache->l2srbar0; in l2cache_init()
596 l2cache->l2srbar0 = l2srbar; in l2cache_init()
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A Dcpu_init_early.c92 ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR; in cpu_init_early_f() local
148 out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR); in cpu_init_early_f()
150 out_be32(&l2cache->l2errdis, in cpu_init_early_f()
153 out_be32(&l2cache->l2ctl, in cpu_init_early_f()
173 clrbits_be32(&l2cache->l2ctl, in cpu_init_early_f()
176 out_be32(&l2cache->l2srbar0, 0x0); in cpu_init_early_f()
A Dfdt.c224 volatile ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR; in l2cache_size() local
225 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; in l2cache_size()
300 struct ccsr_cluster_l2 *l2cache = in ft_fixup_l2cache() local
302 u32 l2cfg0 = in_be32(&l2cache->l2cfg0); in ft_fixup_l2cache()
/arch/riscv/dts/
A Dfu540-c000.dtsi57 next-level-cache = <&l2cache>;
81 next-level-cache = <&l2cache>;
105 next-level-cache = <&l2cache>;
129 next-level-cache = <&l2cache>;
260 l2cache: cache-controller@2010000 { label
A Dfu540-c000-u-boot.dtsi107 &l2cache {

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