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/arch/arm/dts/
A Dsun50i-h5-cpu-opp.dtsi12 clock-latency-ns = <244144>; /* 8 32k periods */
18 clock-latency-ns = <244144>; /* 8 32k periods */
24 clock-latency-ns = <244144>; /* 8 32k periods */
30 clock-latency-ns = <244144>; /* 8 32k periods */
36 clock-latency-ns = <244144>; /* 8 32k periods */
42 clock-latency-ns = <244144>; /* 8 32k periods */
48 clock-latency-ns = <244144>; /* 8 32k periods */
54 clock-latency-ns = <244144>; /* 8 32k periods */
60 clock-latency-ns = <244144>; /* 8 32k periods */
A Dsun50i-a64-cpu-opp.dtsi14 clock-latency-ns = <244144>; /* 8 32k periods */
20 clock-latency-ns = <244144>; /* 8 32k periods */
26 clock-latency-ns = <244144>; /* 8 32k periods */
32 clock-latency-ns = <244144>; /* 8 32k periods */
38 clock-latency-ns = <244144>; /* 8 32k periods */
44 clock-latency-ns = <244144>; /* 8 32k periods */
50 clock-latency-ns = <244144>; /* 8 32k periods */
56 clock-latency-ns = <244144>; /* 8 32k periods */
A Dsun50i-h6-cpu-opp.dtsi12 clock-latency-ns = <244144>; /* 8 32k periods */
21 clock-latency-ns = <244144>; /* 8 32k periods */
30 clock-latency-ns = <244144>; /* 8 32k periods */
39 clock-latency-ns = <244144>; /* 8 32k periods */
48 clock-latency-ns = <244144>; /* 8 32k periods */
57 clock-latency-ns = <244144>; /* 8 32k periods */
66 clock-latency-ns = <244144>; /* 8 32k periods */
75 clock-latency-ns = <244144>; /* 8 32k periods */
84 clock-latency-ns = <244144>; /* 8 32k periods */
93 clock-latency-ns = <244144>; /* 8 32k periods */
A Dsun8i-r40-cpu-opp.dtsi9 clock-latency-ns = <2000000>;
15 clock-latency-ns = <2000000>;
21 clock-latency-ns = <2000000>;
27 clock-latency-ns = <2000000>;
33 clock-latency-ns = <2000000>;
A Dfsl-imx8-ca53.dtsi27 entry-latency-us = <700>;
28 exit-latency-us = <250>;
36 entry-latency-us = <1000>;
37 exit-latency-us = <700>;
39 wakeup-latency-us = <1500>;
A Dvf610.dtsi17 arm,data-latency = <3 3 3>;
18 arm,tag-latency = <2 2 2>;
A Dsun8i-a33.dtsi56 clock-latency-ns = <244144>; /* 8 32k periods */
62 clock-latency-ns = <244144>; /* 8 32k periods */
68 clock-latency-ns = <244144>; /* 8 32k periods */
74 clock-latency-ns = <244144>; /* 8 32k periods */
80 clock-latency-ns = <244144>; /* 8 32k periods */
86 clock-latency-ns = <244144>; /* 8 32k periods */
92 clock-latency-ns = <244144>; /* 8 32k periods */
98 clock-latency-ns = <244144>; /* 8 32k periods */
104 clock-latency-ns = <244144>; /* 8 32k periods */
110 clock-latency-ns = <244144>; /* 8 32k periods */
[all …]
A Duniphier-pro5.dtsi46 clock-latency-ns = <300>;
50 clock-latency-ns = <300>;
54 clock-latency-ns = <300>;
58 clock-latency-ns = <300>;
62 clock-latency-ns = <300>;
66 clock-latency-ns = <300>;
70 clock-latency-ns = <300>;
74 clock-latency-ns = <300>;
78 clock-latency-ns = <300>;
82 clock-latency-ns = <300>;
[all …]
A Duniphier-ld20.dtsi102 clock-latency-ns = <300>;
106 clock-latency-ns = <300>;
110 clock-latency-ns = <300>;
114 clock-latency-ns = <300>;
118 clock-latency-ns = <300>;
122 clock-latency-ns = <300>;
126 clock-latency-ns = <300>;
130 clock-latency-ns = <300>;
140 clock-latency-ns = <300>;
144 clock-latency-ns = <300>;
[all …]
A Dhi3660.dtsi171 entry-latency-us = <400>;
172 exit-latency-us = <650>;
179 entry-latency-us = <500>;
180 exit-latency-us = <1600>;
189 entry-latency-us = <400>;
190 exit-latency-us = <550>;
198 entry-latency-us = <800>;
199 exit-latency-us = <2900>;
220 clock-latency-ns = <300000>;
226 clock-latency-ns = <300000>;
[all …]
A Djuno-r2.dts73 entry-latency-us = <300>;
74 exit-latency-us = <1200>;
82 entry-latency-us = <400>;
83 exit-latency-us = <1200>;
A Dsun50i-h5.dtsi19 clock-latency-ns = <244144>; /* 8 32k periods */
29 clock-latency-ns = <244144>; /* 8 32k periods */
39 clock-latency-ns = <244144>; /* 8 32k periods */
49 clock-latency-ns = <244144>; /* 8 32k periods */
A Dsun8i-a83t.dtsi210 clock-latency-ns = <244144>; /* 8 32k periods */
216 clock-latency-ns = <244144>; /* 8 32k periods */
222 clock-latency-ns = <244144>; /* 8 32k periods */
228 clock-latency-ns = <244144>; /* 8 32k periods */
234 clock-latency-ns = <244144>; /* 8 32k periods */
240 clock-latency-ns = <244144>; /* 8 32k periods */
246 clock-latency-ns = <244144>; /* 8 32k periods */
252 clock-latency-ns = <244144>; /* 8 32k periods */
263 clock-latency-ns = <244144>; /* 8 32k periods */
269 clock-latency-ns = <244144>; /* 8 32k periods */
[all …]
A Darmada-xp-98dx3336.dtsi23 clock-latency = <1000000>;
A Drk3229.dtsi20 clock-latency-ns = <40000>;
A Duniphier-ld11.dtsi64 clock-latency-ns = <300>;
68 clock-latency-ns = <300>;
72 clock-latency-ns = <300>;
76 clock-latency-ns = <300>;
80 clock-latency-ns = <300>;
84 clock-latency-ns = <300>;
88 clock-latency-ns = <300>;
A Dimx7d.dtsi52 clock-latency-ns = <150000>;
60 clock-latency-ns = <150000>;
68 clock-latency-ns = <150000>;
A Darmada-xp-98dx4251.dtsi23 clock-latency = <1000000>;
A Dimx6q.dtsi40 clock-latency = <61036>; /* two CLK32 periods */
77 clock-latency = <61036>; /* two CLK32 periods */
112 clock-latency = <61036>; /* two CLK32 periods */
147 clock-latency = <61036>; /* two CLK32 periods */
A Duniphier-pxs2.dtsi72 clock-latency-ns = <300>;
76 clock-latency-ns = <300>;
80 clock-latency-ns = <300>;
84 clock-latency-ns = <300>;
88 clock-latency-ns = <300>;
92 clock-latency-ns = <300>;
96 clock-latency-ns = <300>;
100 clock-latency-ns = <300>;
/arch/arm/mach-npcm/npcm7xx/
A Dl2_cache_pl310_init.S34 @ Set tag RAM latency
35 @ 1 cycle RAM write access latency
36 @ 1 cycle RAM read access latency
37 @ 1 cycle RAM setup latency
41 @ Set Data RAM latency
42 @ 1 cycle RAM write access latency
43 @ 2 cycles RAM read access latency
44 @ 1 cycle RAM setup latency
/arch/arm/mach-uniphier/dram/
A Dumc-pxs2.c414 int latency; in umc_set_system_latency() local
418 latency += (val & UMC_RDATACTL_RAD2LTY_MASK) >> in umc_set_system_latency()
424 latency += phy_latency & ~1; in umc_set_system_latency()
427 if (latency > 0xf) { in umc_set_system_latency()
429 val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT; in umc_set_system_latency()
431 val |= latency << UMC_RDATACTL_RADLTY_SHIFT; in umc_set_system_latency()
469 int latency; in umc_dc_init() local
496 latency = 12; in umc_dc_init()
499 latency += 2; in umc_dc_init()
501 if (latency > 0xf) { in umc_dc_init()
[all …]
/arch/x86/cpu/apollolake/
A Dcpu.c34 .latency = 1,
41 .latency = 50,
50 .latency = 150,
/arch/arm/include/asm/arch-stm32/
A Dstm32f.h18 void stm32_flash_latency_cfg(int latency);
/arch/x86/include/asm/
A Dsfi.h87 u32 latency; /* latency in ms */ member
96 u32 latency; /* transition latency in ms */ member

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