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Searched refs:m_div (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-lpc32xx/
A Dclk.c25 u32 val, m_div, n_div, p_div; in get_hclk_pll_rate() local
39 m_div = ((val & CLK_HCLK_PLL_FEEDBACK_DIV_MASK) >> 1) + 1; in get_hclk_pll_rate()
56 fcco = fref * m_div; in get_hclk_pll_rate()
/arch/arm/mach-exynos/include/mach/
A Dclock.h1359 unsigned int m_div; /* m divider value */ member
/arch/arm/mach-exynos/
A Dclock.c1296 epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT; in exynos5_set_epll_clk()

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