| /arch/arm/mach-at91/ |
| A D | sdram.c | 36 writel(AT91_SDRAMC_MODE_NOP, ®->mr); in sdramc_initialize()
40 writel(AT91_SDRAMC_MODE_PRECHARGE, ®->mr); in sdramc_initialize()
48 writel(AT91_SDRAMC_MODE_REFRESH, ®->mr); in sdramc_initialize()
56 writel(AT91_SDRAMC_MODE_LMR, ®->mr); in sdramc_initialize()
64 writel(AT91_SDRAMC_MODE_NORMAL, ®->mr); in sdramc_initialize()
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| A D | phy.c | 29 erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; in at91_phy_reset()
38 AT91_RSTC_MR_URSTEN, &rstc->mr); in at91_phy_reset()
56 writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); in at91_phy_reset()
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| /arch/arm/mach-imx/imx8/ |
| A D | cpu.c | 492 owned = sc_rm_is_memreg_owned(-1, mr); in get_owned_memreg()
522 sc_rm_mr_t mr; in get_effective_memsize() local
532 for (mr = 0; mr < 64; mr++) { in get_effective_memsize()
533 err = get_owned_memreg(mr, &start, &end); in get_effective_memsize()
559 sc_rm_mr_t mr; in dram_init() local
570 for (mr = 0; mr < 64; mr++) { in dram_init()
571 err = get_owned_memreg(mr, &start, &end); in dram_init()
626 sc_rm_mr_t mr; in dram_init_banksize() local
638 for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) { in dram_init_banksize()
732 sc_rm_mr_t mr; in enable_caches() local
[all …]
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| A D | ahab.c | 60 sc_rm_mr_t mr; in ahab_verify_cntr_image() local
68 err = sc_rm_find_memreg(-1, &mr, in ahab_verify_cntr_image()
78 err = sc_rm_get_memreg_info(-1, mr, &start, &end); in ahab_verify_cntr_image()
80 debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end); in ahab_verify_cntr_image()
82 err = sc_rm_set_memreg_permissions(-1, mr, in ahab_verify_cntr_image()
98 err = sc_rm_set_memreg_permissions(-1, mr, in ahab_verify_cntr_image()
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| /arch/arm/mach-omap2/ |
| A D | emif-common.c | 62 u32 mr; in get_mr() local
73 if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && in get_mr()
74 ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && in get_mr()
75 ((mr & 0xff000000) >> 24) == (mr & 0xff)) in get_mr()
76 return mr & 0xff; in get_mr()
78 return mr; in get_mr()
1117 u32 mr = 0, temp; in is_lpddr2_sdram_present() local
1120 if (mr > 0xFF) { in is_lpddr2_sdram_present()
1138 if (mr > 0xFF) { in is_lpddr2_sdram_present()
1144 if (mr > 0xFF) { in is_lpddr2_sdram_present()
[all …]
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| /arch/arm/mach-sunxi/ |
| A D | dram_sun9i.c | 362 u16 mr[4] = { 0, }; in mctl_channel_init() local
462 mr[1] = DDR3_MR1_RTT120OHM; in mctl_channel_init()
463 mr[2] = DDR3_MR2_TWL(CWL); in mctl_channel_init()
464 mr[3] = 0; in mctl_channel_init()
483 writel(MCTL_INIT3_MR(mr[0]) | MCTL_INIT3_EMR(mr[1]), in mctl_channel_init()
485 writel(MCTL_INIT4_EMR2(mr[2]) | MCTL_INIT4_EMR3(mr[3]), in mctl_channel_init()
504 writel(MCTL_INIT3_MR(mr[1]) | MCTL_INIT3_EMR(mr[2]), in mctl_channel_init()
632 writel(mr[0], &mctl_phy->mr0); in mctl_channel_init()
633 writel(mr[1], &mctl_phy->mr1); in mctl_channel_init()
634 writel(mr[2], &mctl_phy->mr2); in mctl_channel_init()
[all …]
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| /arch/arm/mach-omap2/am33xx/ |
| A D | ddr.c | 43 u32 mr; in get_mr() local
48 mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data); in get_mr()
49 debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr); in get_mr()
50 if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && in get_mr()
51 ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && in get_mr()
52 ((mr & 0xff000000) >> 24) == (mr & 0xff)) in get_mr()
53 return mr & 0xff; in get_mr()
55 return mr; in get_mr()
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| /arch/arm/mach-sunxi/dram_timings/ |
| A D | ddr2_v3s.c | 47 writel(0x263, &mctl_ctl->mr[0]); in mctl_set_timing_params()
48 writel(0x4, &mctl_ctl->mr[1]); in mctl_set_timing_params()
49 writel(0x0, &mctl_ctl->mr[2]); in mctl_set_timing_params()
50 writel(0x0, &mctl_ctl->mr[3]); in mctl_set_timing_params()
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| A D | ddr3_1333.c | 47 writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */ in mctl_set_timing_params()
48 writel(0x40, &mctl_ctl->mr[1]); in mctl_set_timing_params()
49 writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */ in mctl_set_timing_params()
50 writel(0x0, &mctl_ctl->mr[3]); in mctl_set_timing_params()
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| A D | lpddr3_stock.c | 47 writel(0xc3, &mctl_ctl->mr[1]); /* nWR=8, BL8 */ in mctl_set_timing_params()
48 writel(0xa, &mctl_ctl->mr[2]); /* RL=12, WL=6 */ in mctl_set_timing_params()
49 writel(0x2, &mctl_ctl->mr[3]); /* 40 0hms PD/PU */ in mctl_set_timing_params()
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| /arch/arm/mach-omap2/omap3/ |
| A D | sdrc.c | 41 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) in is_mem_sdr()
113 writel(timings->mr, &sdrc_base->cs[cs].mr); in write_sdrc_timings()
188 timings.mr = readl(&sdrc_base->cs[CS0].mr); in do_sdrc_init()
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| /arch/arm/mach-at91/include/mach/ |
| A D | at91_mc.h | 31 u32 mr; /* 0x00 SDRAMC Mode Register */ member
63 u32 mr; /* 0x00 SDRAMC Mode Register */ member
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| A D | at91_pit.h | 16 u32 mr; /* 0x00 Mode Register */ member
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| A D | at91_rstc.h | 24 u32 mr; /* Reset Controller Mode Register */ member
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| A D | at91_wdt.h | 29 u32 mr; member
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| A D | atmel_mpddrc.h | 14 u32 mr; member
31 u32 mr; /* 0x00: Mode Register */ member
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| /arch/sandbox/cpu/ |
| A D | eth-raw-os.c | 73 struct packet_mreq mr; in _raw_packet_start() local
116 mr.mr_ifindex = device->sll_ifindex; in _raw_packet_start()
117 mr.mr_type = PACKET_MR_PROMISC; in _raw_packet_start()
119 &mr, sizeof(mr)); in _raw_packet_start()
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| /arch/powerpc/cpu/mpc8xx/ |
| A D | start.S | 336 mr r1, r3 /* Set new stack pointer */
337 mr r9, r4 /* Save copy of Global Data pointer */
338 mr r10, r5 /* Save copy of Destination Address */
341 mr r3, r5 /* Destination Address */
397 mr r4,r3
403 mr r4,r3
478 mr r3, r9 /* Global Data pointer */
479 mr r4, r10 /* Destination Address */
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| /arch/powerpc/include/asm/ |
| A D | fsl_dma.h | 15 uint mr; /* DMA mode register */ member
49 uint mr; /* DMA mode register */ member
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| /arch/arm/mach-at91/armv7/ |
| A D | timer.c | 50 writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); in timer_init()
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| A D | cpu.c | 47 writel(cpiv + 0x1000, &pit->mr); in arch_preboot_os()
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| /arch/arm/mach-at91/arm926ejs/ |
| A D | timer.c | 46 writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); in timer_init()
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| A D | cpu.c | 39 writel(cpiv + 0x1000, &pit->mr); in arch_preboot_os()
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| /arch/arm/include/asm/arch-aspeed/ |
| A D | sdram_ast2600.h | 46 #define MCR30_SET_MR(mr) ((mr << MCR30_MODE_REG_SEL_SHIFT) | MCR30_SET_MODE_REG) argument
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| /arch/powerpc/lib/ |
| A D | ticks.S | 37 mr r14, r3 /* save tick count */
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