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Searched refs:phy_con1 (Results 1 – 4 of 4) sorted by relevance

/arch/arm/mach-exynos/
A Ddmc_init_ddr3.c178 writel(val, &phy0_ctrl->phy_con1); in ddr3_mem_ctrl_init()
179 writel(val, &phy1_ctrl->phy_con1); in ddr3_mem_ctrl_init()
701 val = readl(&phy0_ctrl->phy_con1); in ddr3_mem_ctrl_init()
703 writel(val, &phy0_ctrl->phy_con1); in ddr3_mem_ctrl_init()
705 val = readl(&phy1_ctrl->phy_con1); in ddr3_mem_ctrl_init()
707 writel(val, &phy1_ctrl->phy_con1); in ddr3_mem_ctrl_init()
735 val = readl(&phy0_ctrl->phy_con1); in ddr3_mem_ctrl_init()
737 writel(val, &phy0_ctrl->phy_con1); in ddr3_mem_ctrl_init()
739 val = readl(&phy1_ctrl->phy_con1); in ddr3_mem_ctrl_init()
741 writel(val, &phy1_ctrl->phy_con1); in ddr3_mem_ctrl_init()
/arch/arm/mach-exynos/include/mach/
A Ddmc.h331 unsigned int phy_con1; member
378 unsigned int phy_con1; member
/arch/arm/mach-imx/mx7/
A Dddr.c95 writel(ddr_phy_regs_val->phy_con1, &ddr_phy_regs->phy_con1); in mx7_dram_cfg()
/arch/arm/include/asm/arch-mx7/
A Dmx7-ddr.h128 u32 phy_con1; /* 0x0004 */ member

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