| /arch/arm/mach-exynos/ |
| A D | clock.c | 652 sel = (sel >> 24) & 0xf; in exynos4_get_pwm_clk()
713 sel = (sel >> (dev_index << 2)) & 0xf; in exynos4_get_uart_clk()
715 if (sel == 0x6) in exynos4_get_uart_clk()
759 sel = (sel >> (dev_index << 2)) & 0xf; in exynos4x12_get_uart_clk()
761 if (sel == 0x6) in exynos4x12_get_uart_clk()
795 sel = (sel >> (dev_index << 2)) & 0xf; in exynos4_get_mmc_clk()
797 if (sel == 0x6) in exynos4_get_mmc_clk()
928 sel = sel & 0xf; in exynos4_get_lcd_clk()
970 sel = sel & 0xf; in exynos5_get_lcd_clk()
1015 if (sel) in exynos5420_get_lcd_clk()
[all …]
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| /arch/mips/include/asm/ |
| A D | mipsregs.h | 1312 if (sel == 0) \
1330 else if (sel == 0) \
1361 if (sel == 0) \
1378 else if (sel == 0) \
1438 if (sel == 0) \
1471 else if (sel == 0) \
1518 : "i" (sel)); \
1970 : "i" (sel)); \
1983 : "i" (sel)); \
1996 "i" (sel)); \
[all …]
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| /arch/arm/cpu/armv7/bcm235xx/ |
| A D | clk-core.c | 120 if (selector_exists(&cd->sel)) { in peri_clk_enable()
121 reg = readl(base + cd->sel.offset); in peri_clk_enable()
122 bitfield_replace(reg, cd->sel.shift, cd->sel.width, in peri_clk_enable()
123 c->sel); in peri_clk_enable()
124 writel(reg, base + cd->sel.offset); in peri_clk_enable()
191 c->sel = i; in peri_clk_set_rate()
215 if (selector_exists(&cd->sel)) { in peri_clk_get_rate()
216 reg = readl(base + cd->sel.offset); in peri_clk_get_rate()
217 c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width); in peri_clk_get_rate()
223 c->sel = 0; in peri_clk_get_rate()
[all …]
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| A D | clk-bcm235xx.c | 149 .sel = SELECTOR(0x0a28, 0, 3),
161 .sel = SELECTOR(0x0a2c, 0, 3),
173 .sel = SELECTOR(0x0a34, 0, 3),
185 .sel = SELECTOR(0x0a30, 0, 3),
238 .sel = SELECTOR(0x0a64, 0, 3),
249 .sel = SELECTOR(0x0a68, 0, 3),
260 .sel = SELECTOR(0x0a84, 0, 3),
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| A D | clk-core.h | 71 int sel; member
110 #define selector_exists(sel) ((sel)->width != 0) argument
404 struct bcm_clk_sel sel; member
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| /arch/arm/cpu/armv7/bcm281xx/ |
| A D | clk-core.c | 120 if (selector_exists(&cd->sel)) { in peri_clk_enable()
121 reg = readl(base + cd->sel.offset); in peri_clk_enable()
122 bitfield_replace(reg, cd->sel.shift, cd->sel.width, in peri_clk_enable()
123 c->sel); in peri_clk_enable()
124 writel(reg, base + cd->sel.offset); in peri_clk_enable()
191 c->sel = i; in peri_clk_set_rate()
215 if (selector_exists(&cd->sel)) { in peri_clk_get_rate()
216 reg = readl(base + cd->sel.offset); in peri_clk_get_rate()
217 c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width); in peri_clk_get_rate()
223 c->sel = 0; in peri_clk_get_rate()
[all …]
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| A D | clk-bcm281xx.c | 149 .sel = SELECTOR(0x0a28, 0, 3),
161 .sel = SELECTOR(0x0a2c, 0, 3),
173 .sel = SELECTOR(0x0a34, 0, 3),
185 .sel = SELECTOR(0x0a30, 0, 3),
238 .sel = SELECTOR(0x0a64, 0, 3),
249 .sel = SELECTOR(0x0a68, 0, 3),
260 .sel = SELECTOR(0x0a84, 0, 3),
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| A D | clk-core.h | 71 int sel; member
110 #define selector_exists(sel) ((sel)->width != 0) argument
404 struct bcm_clk_sel sel; member
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| /arch/arm/mach-imx/ |
| A D | cmd_mfgprot.c | 33 char *pubk, *sign, *sel; in do_mfgprot() local
39 sel = argv[1]; in do_mfgprot()
50 if (strcmp(sel, pubk) == 0) { in do_mfgprot()
68 } else if (strcmp(sel, sign) == 0) { in do_mfgprot()
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| /arch/arm/dts/ |
| A D | mt7987a-u-boot.dtsi | 55 clock-names = "spi-clk", "sel-clk";
62 clock-names = "spi-clk", "sel-clk";
69 clock-names = "spi-clk", "sel-clk";
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| A D | k3-am654-r5-base-board.dts | 150 cpsw-phy-sel@40f04040 {
151 compatible = "ti,am654-cpsw-phy-sel";
153 reg-names = "gmii-sel";
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| A D | ca-presidio-engboard.dts | 92 blink-sel =<0>;
101 blink-sel =<1>;
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| A D | socfpga_cyclone5_mcvevk.dts | 64 ts,ref-sel = <0>;
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| A D | imx8mn-var-som-symphony.dts | 77 usb3-sata-sel-hog {
91 enet-sel-hog {
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| A D | socfpga_agilex5_socdk-u-boot.dtsi | 115 cdns,phy-rd-del-sel = <52>;
119 cdns,phy-param-phase-detect-sel = <2>;
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| A D | imx53-m53.dtsi | 62 st,ref-sel = <0>;
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| A D | mt7981.dtsi | 270 clock-names = "spi-clk", "sel-clk";
285 clock-names = "spi-clk", "sel-clk";
298 clock-names = "spi-clk", "sel-clk";
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| A D | imx6ul-phytec-segin-peb-av-02.dtsi | 68 st,ref-sel = <0>;
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| /arch/arm/mach-kirkwood/ |
| A D | mpp.c | 53 unsigned int sel = MPP_SEL(*mpp_list); in kirkwood_mpp_conf() local
77 mpp_ctrl[num / 8] |= sel << shift; in kirkwood_mpp_conf()
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| /arch/mips/cpu/ |
| A D | start.S | 25 .macro init_wr sel
26 MTC0 zero, CP0_WATCHLO,\sel
27 mtc0 t1, CP0_WATCHHI,\sel
28 mfc0 t0, CP0_WATCHHI,\sel
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| /arch/mips/mach-mtmips/mt7621/tpl/ |
| A D | start.S | 21 .macro init_wr sel
22 MTC0 zero, CP0_WATCHLO,\sel
23 mtc0 t1, CP0_WATCHHI,\sel
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| /arch/arm/mach-tegra/ |
| A D | cpu.c | 277 struct clk_pll_table *sel; in init_pllx() local
297 sel = &tegra_pll_x_table[chip_sku][osc]; in init_pllx()
298 pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon); in init_pllx()
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| /arch/arm/include/asm/arch-sunxi/ |
| A D | tve.h | 78 #define SUNXI_TVE_GCTRL_DAC_INPUT(dac, sel) ((sel) << (((dac) + 1) * 4)) argument
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| /arch/mips/mach-mtmips/mt7621/spl/ |
| A D | start.S | 27 .macro init_wr sel
28 MTC0 zero, CP0_WATCHLO,\sel
29 mtc0 t1, CP0_WATCHHI,\sel
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| /arch/powerpc/cpu/mpc85xx/ |
| A D | fsl_corenet2_serdes.c | 209 u32 sfp_spfr0, sel; in serdes_init() local
228 sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK; in serdes_init()
230 if (has_erratum_a007186() && (sel == 0x01 || sel == 0x02)) { in serdes_init()
|