Searched refs:timing (Results 1 – 25 of 95) sorted by relevance
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| /arch/arm/dts/ |
| A D | rk3288-veyron-jerry-u-boot.dtsi | 6 rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
11 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
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| A D | rk3288-veyron-minnie-u-boot.dtsi | 6 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
11 rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
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| A D | rk3288-veyron-mickey-u-boot.dtsi | 6 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
11 rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
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| A D | rk3288-rock2-square-u-boot.dtsi | 6 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
11 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
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| A D | rk3229-evb-u-boot.dtsi | 12 rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3
17 rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>;
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| A D | rk3288-veyron-speedy-u-boot.dtsi | 23 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
28 rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
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| A D | rk3288-rock-pi-n8-u-boot.dtsi | 15 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
20 rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
|
| A D | rk3288-vyasa-u-boot.dtsi | 9 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
14 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
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| A D | rk3288-evb-u-boot.dtsi | 9 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
14 rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
|
| A D | rk3288-popmetal-u-boot.dtsi | 9 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
14 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
|
| A D | exynos5250-arndale.dts | 32 samsung,dw-mshc-sdr-timing = <1 3>;
42 samsung,dw-mshc-sdr-timing = <1 2>;
|
| A D | rk3066a-mk808-u-boot.dtsi | 17 rockchip,pctl-timing = <0x12c 0xc8 0x1f4 0x1e 0x4e 0x4 0x69 0x6
22 rockchip,phy-timing = <0x208c6690 0x690878 0x10022a00
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| A D | rk3188-radxarock-u-boot.dtsi | 25 rockchip,pctl-timing = <0x12c 0xc8 0x1f4 0x1e 0x4e 0x4 0x69 0x6
30 rockchip,phy-timing = <0x208c6690 0x690878 0x10022a00
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| A D | rk3288-phycore-rdk-u-boot.dtsi | 17 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
22 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
|
| A D | rk3288-tinker-u-boot.dtsi | 9 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
14 rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
|
| A D | rk3288-miqi-u-boot.dtsi | 9 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
14 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
|
| A D | rk3288-firefly-u-boot.dtsi | 15 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
20 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
|
| A D | k3-am654-ddr.dtsi | 79 ti,ctl-timing = <
184 ti,phy-timing = <
|
| A D | imx6dl-colibri-eval-v3.dts | 143 fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
154 fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
|
| A D | stm32mp1-ddr.dtsi | 46 st,ctl-timing = <
81 st,phy-timing = <
|
| A D | tegra20-colibri.dts | 29 timing@0 {
49 nvidia,timing = <15 100 25 80 25 10 15 10 100>;
|
| A D | exynos5420-smdk5420.dts | 111 samsung,dw-mshc-sdr-timing = <1 3>;
123 samsung,dw-mshc-sdr-timing = <1 2>;
|
| A D | stm32f746-disco-u-boot.dtsi | 39 st,sdram-timing = /bits/ 8 <TMRD_2
61 timing@0 {
|
| /arch/arm/mach-omap2/ |
| A D | Kconfig | 143 prompt "Static or dynamic DDR timing calculations"
146 For the DDR timing information we can either dynamically determine
148 dynamic method). Default to the static timing information.
151 bool "Use precalcualted timing values"
154 bool "Use default LPDDR2 timing values"
|
| /arch/mips/mach-mtmips/mt7621/ |
| A D | Kconfig | 30 prompt "DDR2 timing parameters"
51 prompt "DDR3 timing parameters"
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