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Searched refs:PLL (Results 1 – 24 of 24) sorted by relevance

/drivers/clk/at91/
A DKconfig9 PLLA, UTMI PLL. Clocks can also be a source clock of other
16 bool "Support UTMI PLL Clock"
23 This option is used to enable the AT91 UTMI PLL clock
25 output of 480 MHz UTMI PLL, The souce clock of the UTMI
26 PLL is the main clock, so the main clock must select the
35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
59 bool "PLL support for SAM9X60 SoCs"
62 This option is used to enable the AT91 SAM9X60's PLL clock
/drivers/clk/mediatek/
A Dclk-mt8365.c22 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ macro
42 PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001, PLL_AO, 22, 0x0310,
44 PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0xFF000001, HAVE_RST_BAR, 22,
46 PLL(CLK_APMIXED_UNIVPLL, 0x0208, 0x0214, 0xFF000001, HAVE_RST_BAR, 22,
48 PLL(CLK_APMIXED_MFGPLL, 0x0218, 0x0224, 0x00000001, 0, 22, 0x021C, 24,
50 PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001, 0, 22, 0x0354, 24,
52 PLL(CLK_APMIXED_MMPLL, 0x0330, 0x033C, 0x00000001, 0, 22, 0x0334, 24,
54 PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001, 0, 32, 0x0320, 24,
56 PLL(CLK_APMIXED_APLL2, 0x0360, 0x0370, 0x00000001, 0, 32, 0x0364, 24,
60 PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x00000001, 0, 22, 0x0394, 24,
[all …]
A Dclk-mt8183.c40 PLL(CLK_APMIXED_ARMPLL_LL, 0x0200, 0x020C, 0x00000001,
43 PLL(CLK_APMIXED_ARMPLL_L, 0x0210, 0x021C, 0x00000001,
46 PLL(CLK_APMIXED_CCIPLL, 0x0290, 0x029C, 0x00000001,
49 PLL(CLK_APMIXED_MAINPLL, 0x0220, 0x022C, 0x00000001,
52 PLL(CLK_APMIXED_UNIV2PLL, 0x0230, 0x023C, 0x00000001,
55 PLL(CLK_APMIXED_MSDCPLL, 0x0250, 0x025C, 0x00000001,
57 PLL(CLK_APMIXED_MMPLL, 0x0270, 0x027C, 0x00000001,
60 PLL(CLK_APMIXED_MFGPLL, 0x0240, 0x024C, 0x00000001,
62 PLL(CLK_APMIXED_TVDPLL, 0x0260, 0x026C, 0x00000001,
64 PLL(CLK_APMIXED_APLL1, 0x02A0, 0x02B0, 0x00000001,
[all …]
A Dclk-mt8512.c21 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ macro
41 PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001,
43 PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0x00000001,
45 PLL(CLK_APMIXED_UNIVPLL2, 0x0208, 0x0214, 0x00000001,
47 PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001,
49 PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001,
51 PLL(CLK_APMIXED_APLL2, 0x0360, 0x0370, 0x00000001,
53 PLL(CLK_APMIXED_IPPLL, 0x0374, 0x0380, 0x00000001,
55 PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x00000001,
57 PLL(CLK_APMIXED_TCONPLL, 0x03A0, 0x03AC, 0x00000001,
A Dclk-mt7623.c61 PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x80000001, 0,
67 PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x00000001, 0,
69 PLL(CLK_APMIXED_MSDCPLL, 0x240, 0x24c, 0x00000001, 0,
71 PLL(CLK_APMIXED_TVDPLL, 0x250, 0x25c, 0x00000001, 0,
73 PLL(CLK_APMIXED_AUD1PLL, 0x270, 0x27c, 0x00000001, 0,
75 PLL(CLK_APMIXED_TRGPLL, 0x280, 0x28c, 0x00000001, 0,
77 PLL(CLK_APMIXED_ETHPLL, 0x290, 0x29c, 0x00000001, 0,
79 PLL(CLK_APMIXED_VDECPLL, 0x2a0, 0x2ac, 0x00000001, 0,
81 PLL(CLK_APMIXED_HADDS2PLL, 0x2b0, 0x2bc, 0x00000001, 0,
83 PLL(CLK_APMIXED_AUD2PLL, 0x2c0, 0x2cc, 0x00000001, 0,
[all …]
A Dclk-mt7622.c32 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ macro
49 PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
51 PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
53 PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
55 PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
57 PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
59 PLL(CLK_APMIXED_AUD1PLL, 0x324, 0x330, 0x1, 0,
61 PLL(CLK_APMIXED_AUD2PLL, 0x334, 0x340, 0x1, 0,
63 PLL(CLK_APMIXED_TRGPLL, 0x344, 0x354, 0x1, 0,
65 PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
A Dclk-mt8516.c20 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ macro
37 PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001, 0,
39 PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
41 PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
43 PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001, 0,
45 PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, 0,
47 PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001, 0,
A Dclk-mt7629.c32 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ macro
49 PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
51 PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
53 PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
55 PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
57 PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
59 PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
A Dclk-mt8518.c20 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ macro
37 PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001,
39 PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
41 PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
43 PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001,
45 PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001,
47 PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001,
49 PLL(CLK_APMIXED_TVDPLL, 0x01C0, 0x01D0, 0x00000001,
/drivers/clk/ti/
A DKconfig46 bool "PLL clock support for K3 SoC family of devices"
49 Enables PLL clock support for K3 SoC family of devices.
52 bool "PLL clock support for K3 SoC family of devices"
55 Enables PLL clock support for K3 SoC family of devices.
/drivers/clk/adi/
A DKconfig33 Modifying PLL configuration is not supported; that must be done prior
52 Modifying PLL configuration is not supported; that must be done prior
67 Modifying PLL configuration is not supported; that must be done prior
82 Modifying PLL configuration is not supported; that must be done prior
/drivers/clk/exynos/
A Dclk-exynos850.c99 PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "clock-oscclk",
101 PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "clock-oscclk",
103 PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "clock-oscclk",
A Dclk.h198 #define PLL(_typ, _id, _name, _pname, _con) \ macro
/drivers/ddr/imx/imx8ulp/
A DKconfig8 bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK"
/drivers/clk/rockchip/
A Dclk_rk3588.c48 [B0PLL] = PLL(pll_rk3588, PLL_B0PLL, RK3588_B0_PLL_CON(0),
51 [B1PLL] = PLL(pll_rk3588, PLL_B1PLL, RK3588_B1_PLL_CON(8),
54 [LPLL] = PLL(pll_rk3588, PLL_LPLL, RK3588_LPLL_CON(16),
56 [V0PLL] = PLL(pll_rk3588, PLL_V0PLL, RK3588_PLL_CON(88),
58 [AUPLL] = PLL(pll_rk3588, PLL_AUPLL, RK3588_PLL_CON(96),
60 [CPLL] = PLL(pll_rk3588, PLL_CPLL, RK3588_PLL_CON(104),
62 [GPLL] = PLL(pll_rk3588, PLL_GPLL, RK3588_PLL_CON(112),
64 [NPLL] = PLL(pll_rk3588, PLL_NPLL, RK3588_PLL_CON(120),
66 [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128),
73 [SPLL] = PLL(pll_rk3588, 0, RK3588_SBUSCRU_SPLL_CON(0),
A Dclk_rk3308.c57 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3308_PLL_CON(0),
59 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3308_PLL_CON(8),
61 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
63 [VPLL1] = PLL(pll_rk3328, PLL_VPLL1, RK3308_PLL_CON(24),
A Dclk_rk3568.c76 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3568_PLL_CON(0),
78 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3568_PLL_CON(8),
80 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3568_PLL_CON(24),
82 [GPLL] = PLL(pll_rk3328, PLL_HPLL, RK3568_PLL_CON(16),
84 [NPLL] = PLL(pll_rk3328, PLL_NPLL, RK3568_PLL_CON(32),
86 [VPLL] = PLL(pll_rk3328, PLL_VPLL, RK3568_PLL_CON(40),
88 [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3568_PMU_PLL_CON(0),
90 [HPLL] = PLL(pll_rk3328, PLL_HPLL, RK3568_PMU_PLL_CON(16),
A Dclk_rk3528.c67 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3528_PLL_CON(0),
70 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3528_PLL_CON(8),
73 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3528_PLL_CON(24),
76 [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3528_PCIE_PLL_CON(32),
79 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3528_DDRPHY_PLL_CON(16),
A Dclk_rk3576.c48 [BPLL] = PLL(pll_rk3588, PLL_BPLL, RK3576_PLL_CON(0),
51 [LPLL] = PLL(pll_rk3588, PLL_LPLL, RK3576_LPLL_CON(16),
53 [VPLL] = PLL(pll_rk3588, PLL_VPLL, RK3576_PLL_CON(88),
55 [AUPLL] = PLL(pll_rk3588, PLL_AUPLL, RK3576_PLL_CON(96),
57 [CPLL] = PLL(pll_rk3588, PLL_CPLL, RK3576_PLL_CON(104),
59 [GPLL] = PLL(pll_rk3588, PLL_GPLL, RK3576_PLL_CON(112),
61 [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3576_PMU_PLL_CON(128),
A Dclk_rv1126.c60 [APLL] = PLL(pll_rk3328, PLL_APLL, RV1126_PLL_CON(0),
62 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RV1126_PLL_CON(8),
64 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RV1126_PLL_CON(16),
66 [HPLL] = PLL(pll_rk3328, PLL_HPLL, RV1126_PLL_CON(24),
68 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RV1126_PMU_PLL_CON(0),
/drivers/clk/
A Dclk_k210.c279 #define PLL(_off, _shift, _width) { \ macro
284 [0] = PLL(K210_SYSCTL_PLL0, 0, 2),
285 [1] = PLL(K210_SYSCTL_PLL1, 8, 1),
286 [2] = PLL(K210_SYSCTL_PLL2, 16, 1),
287 #undef PLL
A DKconfig164 bool "Enable setting the Kendryte K210 PLL rate"
/drivers/power/
A DKconfig277 On A83T / H8 boards aldo2 powers VDD-DLL, VCC18-PLL, CPVDD, VDD18-ADC,
289 On A23 / A31 / A33 / R40 boards aldo3 is VCC-PLL and AVCC and should
/drivers/video/
A DKconfig662 parallel LCD interface instead of TX_CLK as the PLL clock source.

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