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Searched refs:PS (Results 1 – 2 of 2) sorted by relevance

/drivers/ddr/marvell/axp/
A Dddr3_read_leveling.c359 info->rl_val[cs][idx][PS] = phase; in overrun()
689 if (dram_info->rl_val[cs][pup][PS] < phase_min) in ddr3_read_leveling_single_cs_rl_mode()
690 phase_min = dram_info->rl_val[cs][pup][PS]; in ddr3_read_leveling_single_cs_rl_mode()
877 dram_info->rl_val[cs][idx][PS] = in ddr3_read_leveling_single_cs_window_mode()
1095 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][PS], 1); in ddr3_read_leveling_single_cs_window_mode()
1110 if (dram_info->rl_val[cs][idx][PS] == 4) in ddr3_read_leveling_single_cs_window_mode()
1111 dram_info->rl_val[cs][idx][PS] = 1; in ddr3_read_leveling_single_cs_window_mode()
1115 delay_s = dram_info->rl_val[cs][idx][PS] * in ddr3_read_leveling_single_cs_window_mode()
1132 delay_s = dram_info->rl_val[cs][idx][PS] * in ddr3_read_leveling_single_cs_window_mode()
1148 if (dram_info->rl_val[cs][idx][PS] > 1) in ddr3_read_leveling_single_cs_window_mode()
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A Dddr3_hw_training.h116 #define PS 2 macro

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