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Searched refs:ccm (Results 1 – 8 of 8) sorted by relevance

/drivers/video/sunxi/
A Dsunxi_display.c102 struct sunxi_ccm_reg * const ccm = in sunxi_hdmi_hpd_detect() local
122 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); in sunxi_hdmi_hpd_detect()
144 struct sunxi_ccm_reg * const ccm = in sunxi_hdmi_shutdown() local
234 struct sunxi_ccm_reg * const ccm = in sunxi_hdmi_edid_get_mode() local
357 struct sunxi_ccm_reg * const ccm = in sunxi_frontend_init() local
450 struct sunxi_ccm_reg * const ccm = in sunxi_composer_init() local
536 struct sunxi_ccm_reg * const ccm = in sunxi_lcdc_init() local
634 struct sunxi_ccm_reg * const ccm = local
671 struct sunxi_ccm_reg * const ccm = local
806 struct sunxi_ccm_reg * const ccm = local
[all …]
A Dsunxi_dw_hdmi.c241 struct sunxi_ccm_reg * const ccm = in sunxi_dw_hdmi_lcdc_init() local
250 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0); in sunxi_dw_hdmi_lcdc_init()
253 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0); in sunxi_dw_hdmi_lcdc_init()
255 &ccm->lcd0_clk_cfg); in sunxi_dw_hdmi_lcdc_init()
260 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1); in sunxi_dw_hdmi_lcdc_init()
263 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1); in sunxi_dw_hdmi_lcdc_init()
265 &ccm->lcd1_clk_cfg); in sunxi_dw_hdmi_lcdc_init()
333 struct sunxi_ccm_reg * const ccm = in sunxi_dw_hdmi_probe() local
344 clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK, in sunxi_dw_hdmi_probe()
348 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2); in sunxi_dw_hdmi_probe()
A Dsunxi_lcd.c41 struct sunxi_ccm_reg * const ccm = in sunxi_lcd_enable() local
50 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0); in sunxi_lcd_enable()
52 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0); in sunxi_lcd_enable()
56 lcdc_pll_set(ccm, 0, edid->pixelclock.typ / 1000, in sunxi_lcd_enable()
A Dlcdc.c212 void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock, in lcdc_pll_set() argument
315 &ccm->lcd0_ch0_clk_cfg); in lcdc_pll_set()
318 &ccm->lcd0_clk_cfg); in lcdc_pll_set()
326 CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg); in lcdc_pll_set()
328 setbits_le32(&ccm->lcd0_ch1_clk_cfg, in lcdc_pll_set()
A Dsunxi_de2.c35 struct sunxi_ccm_reg * const ccm = in sunxi_de2_composer_init() local
50 clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK, in sunxi_de2_composer_init()
54 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE); in sunxi_de2_composer_init()
55 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE); in sunxi_de2_composer_init()
58 setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE); in sunxi_de2_composer_init()
/drivers/mmc/
A Dsunxi_mmc.c498 void *ccm = (void *)SUNXI_CCM_BASE; in mmc_resource_init() local
505 priv->mclkreg = ccm + CCU_MMC0_CLK_CFG; in mmc_resource_init()
509 priv->mclkreg = ccm + CCU_MMC1_CLK_CFG; in mmc_resource_init()
514 priv->mclkreg = ccm + CCU_MMC2_CLK_CFG; in mmc_resource_init()
520 priv->mclkreg = ccm + CCU_MMC3_CLK_CFG; in mmc_resource_init()
565 void *ccm = (void *)SUNXI_CCM_BASE; in sunxi_mmc_init() local
595 setbits_le32(ccm + CCU_AHB_GATE0, 1 << AHB_GATE_OFFSET_MMC(sdc_no)); in sunxi_mmc_init()
599 setbits_le32(ccm + CCU_AHB_RESET0_CFG, 1 << AHB_RESET_OFFSET_MMC(sdc_no)); in sunxi_mmc_init()
607 setbits_le32(ccm + CCU_H6_MMC_GATE_RESET, 1 << sdc_no); in sunxi_mmc_init()
609 setbits_le32(ccm + CCU_H6_MMC_GATE_RESET, 1 << (RESET_SHIFT + sdc_no)); in sunxi_mmc_init()
/drivers/mtd/nand/raw/
A Dsunxi_nand_spl.c544 struct sunxi_ccm_reg *const ccm = in nand_deselect() local
547 clrbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); in nand_deselect()
549 clrbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); in nand_deselect()
551 clrbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); in nand_deselect()
553 clrbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); in nand_deselect()
A Dsunxi_nand.c294 struct sunxi_ccm_reg *const ccm = in sunxi_nfc_set_clk_rate() local
310 &ccm->nand0_clk_cfg); in sunxi_nfc_set_clk_rate()
313 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0)); in sunxi_nfc_set_clk_rate()
315 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); in sunxi_nfc_set_clk_rate()
317 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); in sunxi_nfc_set_clk_rate()

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