Searched refs:cs0_config (Results 1 – 6 of 6) sorted by relevance
| /drivers/ddr/fsl/ |
| A D | util.c | 191 uint32_t cs0_config = ddr_in32(&ddr->cs0_config); in print_ddr_info() local
282 if ((cs0_config & 0x20000000) && (start_ctrl == 0)) { in print_ddr_info()
286 switch ((cs0_config >> 24) & 0xf) { in print_ddr_info()
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| A D | fsl_ddr_gen4.c | 73 u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config; in fsl_ddr_set_memctl_regs() local
128 ddr_out32(&ddr->cs0_config, in fsl_ddr_set_memctl_regs()
133 ddr_out32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
550 ddr_out32(&ddr->cs0_config, regs->cs[0].config); in fsl_ddr_set_memctl_regs()
576 cs0_config = ddr_in32(&ddr->cs0_config); in fsl_ddr_set_memctl_regs()
581 if (cs0_config & CTLR_INTLV_MASK) { in fsl_ddr_set_memctl_regs()
621 if (cs0_config & CTLR_INTLV_MASK) { in fsl_ddr_set_memctl_regs()
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| A D | mpc85xx_ddr_gen1.c | 31 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
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| A D | mpc85xx_ddr_gen2.c | 51 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
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| A D | arm_ddr_gen3.c | 72 ddr_out32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
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| A D | mpc85xx_ddr_gen3.c | 106 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
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