| /drivers/led/ |
| A D | led_lp5562.c | 340 u8 opcode = 0; in lp5562_led_set_period() local 374 program[opcode++] = in lp5562_led_set_period() 379 program[opcode++] = in lp5562_led_set_period() 385 program[opcode++] = in lp5562_led_set_period() 389 program[opcode++] = in lp5562_led_set_period() 402 program[opcode++] = in lp5562_led_set_period() 408 program[opcode++] = in lp5562_led_set_period() 414 program[opcode++] = in lp5562_led_set_period() 421 program[opcode++] = in lp5562_led_set_period() 428 program[opcode++] = in lp5562_led_set_period() [all …]
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| /drivers/spi/ |
| A D | cadence_qspi_apb.c | 468 u8 opcode; in cadence_qspi_apb_command_read() local 471 opcode = op->cmd.opcode >> 8; in cadence_qspi_apb_command_read() 473 opcode = op->cmd.opcode; in cadence_qspi_apb_command_read() 559 u8 opcode; in cadence_qspi_apb_command_write() local 562 opcode = op->cmd.opcode >> 8; in cadence_qspi_apb_command_write() 564 opcode = op->cmd.opcode; in cadence_qspi_apb_command_write() 622 u8 opcode; in cadence_qspi_apb_read_setup() local 639 opcode = op->cmd.opcode >> 8; in cadence_qspi_apb_read_setup() 641 opcode = op->cmd.opcode; in cadence_qspi_apb_read_setup() 812 opcode = op->cmd.opcode >> 8; in cadence_qspi_apb_write_setup() [all …]
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| A D | bcm63xx_hsspi.c | 260 uint16_t opcode = 0; in bcm63xx_hsspi_xfer_dummy_cs() local 270 opcode = HSSPI_FIFO_OP_READ_WRITE; in bcm63xx_hsspi_xfer_dummy_cs() 272 opcode = HSSPI_FIFO_OP_CODE_R; in bcm63xx_hsspi_xfer_dummy_cs() 274 opcode = HSSPI_FIFO_OP_CODE_W; in bcm63xx_hsspi_xfer_dummy_cs() 276 if (opcode != HSSPI_FIFO_OP_CODE_R) in bcm63xx_hsspi_xfer_dummy_cs() 282 opcode |= HSSPI_FIFO_OP_MBIT_MASK; in bcm63xx_hsspi_xfer_dummy_cs() 401 uint16_t opcode = 0; in bcm63xx_hsspi_xfer_prepend() local 423 opcode = HSSPI_FIFO_OP_CODE_W; in bcm63xx_hsspi_xfer_prepend() 427 opcode = HSSPI_FIFO_OP_CODE_R; in bcm63xx_hsspi_xfer_prepend() 430 opcode = HSSPI_FIFO_OP_READ_WRITE; in bcm63xx_hsspi_xfer_prepend() [all …]
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| A D | ca_sflash.c | 420 struct spi_mem_op *op, u8 opcode) in _ca_sflash_issue_cmd() argument 430 GENMASK(31, 0), CA_SF_AR_ACCODE(opcode)); in _ca_sflash_issue_cmd() 446 GENMASK(31, 0), CA_SF_EAR_OP(op->cmd.opcode) in _ca_sflash_issue_cmd() 458 CA_SF_AR_OP(op->cmd.opcode)); in _ca_sflash_issue_cmd() 462 if (opcode == CA_SF_AC_OP_4_ADDR) { /* erase_op */ in _ca_sflash_issue_cmd() 491 u8 opcode; in ca_sflash_exec_op() local 494 __func__, op->cmd.opcode, op->addr.val, in ca_sflash_exec_op() 498 opcode = CA_SF_AC_OP; in ca_sflash_exec_op() 500 opcode = CA_SF_AC_OP_4_ADDR; in ca_sflash_exec_op() 502 opcode = CA_SF_AC_OP_EXTEND; in ca_sflash_exec_op() [all …]
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| A D | bcmbca_hsspi.c | 219 u16 opcode = 0; in bcmbca_hsspi_xfer() local 230 opcode = HSSPI_FIFO_OP_READ_WRITE; in bcmbca_hsspi_xfer() 232 opcode = HSSPI_FIFO_OP_CODE_R; in bcmbca_hsspi_xfer() 234 opcode = HSSPI_FIFO_OP_CODE_W; in bcmbca_hsspi_xfer() 236 if (opcode != HSSPI_FIFO_OP_CODE_R) in bcmbca_hsspi_xfer() 240 if ((opcode == HSSPI_FIFO_OP_CODE_R && (plat->mode & SPI_RX_DUAL)) || in bcmbca_hsspi_xfer() 241 (opcode == HSSPI_FIFO_OP_CODE_W && (plat->mode & SPI_TX_DUAL))) { in bcmbca_hsspi_xfer() 242 opcode |= HSSPI_FIFO_OP_MBIT_MASK; in bcmbca_hsspi_xfer() 268 writew(cpu_to_be16(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK)), in bcmbca_hsspi_xfer()
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| A D | ich.c | 168 ich_writeb(ctlr, trans->opcode, ctlr->opmenu); in spi_setup_opcode() 179 if (trans->opcode == SPI_OPCODE_WREN) in spi_setup_opcode() 185 if (opmenu[opcode_index] == trans->opcode) in spi_setup_opcode() 190 debug("ICH SPI: Opcode %x not found\n", trans->opcode); in spi_setup_opcode() 279 if (trans->opcode != op->cmd.opcode) in ich_spi_exec_op_swseq() 280 trans->opcode = op->cmd.opcode; in ich_spi_exec_op_swseq() 282 if (lock && trans->opcode == SPI_OPCODE_WRDIS) in ich_spi_exec_op_swseq() 285 if (trans->opcode == SPI_OPCODE_WREN) { in ich_spi_exec_op_swseq() 292 ich_writew(ctlr, trans->opcode, ctlr->preop); in ich_spi_exec_op_swseq() 535 switch (op->cmd.opcode) { in ich_spi_exec_op_hwseq() [all …]
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| A D | cadence_ospi_versal.c | 24 u8 opcode, addr_bytes, *rxbuf, dummy_cycles; in cadence_qspi_apb_dma_read() local 89 opcode = CMD_4BYTE_FAST_READ; in cadence_qspi_apb_dma_read() 101 writel((dummy_cycles << CQSPI_REG_RD_INSTR_DUMMY_LSB) | opcode, in cadence_qspi_apb_dma_read() 104 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; in cadence_qspi_apb_dma_read()
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| A D | airoha_snfi_spi.c | 560 u8 data[8], cmd, opcode = op->cmd.opcode; in airoha_snand_exec_op() local 577 err = airoha_snand_write_data(priv, 0x8, &opcode, sizeof(opcode)); in airoha_snand_exec_op() 582 cmd = opcode == SPI_NAND_OP_GET_FEATURE ? 0x11 : 0x8; in airoha_snand_exec_op()
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| A D | zynq_qspi.c | 739 if (op->cmd.opcode == SPINOR_OP_BE_4K || in update_stripe() 740 op->cmd.opcode == SPINOR_OP_CHIP_ERASE || in update_stripe() 741 op->cmd.opcode == SPINOR_OP_SE || in update_stripe() 742 op->cmd.opcode == SPINOR_OP_WREAR || in update_stripe() 743 op->cmd.opcode == SPINOR_OP_WRSR in update_stripe() 777 op_buf[pos++] = op->cmd.opcode; in zynq_qspi_exec_op()
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| A D | mtk_snor.c | 216 writeb(op->cmd.opcode, priv->base + MTK_NOR_REG_PRGDATA(4)); in mtk_snor_setup_bus() 221 writeb(op->cmd.opcode, priv->base + MTK_NOR_REG_PRGDATA(3)); in mtk_snor_setup_bus() 225 if (op->cmd.opcode == 0x0b) in mtk_snor_setup_bus() 403 txbuf[tx_cnt] = op->cmd.opcode; in mtk_snor_cmd_program() 445 writeb(op->cmd.opcode, priv->base + MTK_NOR_REG_PRGDATA0); in mtk_snor_exec_op()
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| A D | microchip_coreqspi.c | 313 u8 opcode = op->cmd.opcode; in mchp_coreqspi_exec_op() local 326 if (op->cmd.opcode) { in mchp_coreqspi_exec_op() 327 qspi->txbuf = &opcode; in mchp_coreqspi_exec_op()
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| A D | spi-sifive.c | 276 u8 opcode = op->cmd.opcode; in sifive_spi_exec_op() local 289 ret = sifive_spi_xfer(dev, 8, (void *)&opcode, NULL, flags); in sifive_spi_exec_op()
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| /drivers/nvme/ |
| A D | nvme.h | 227 __u8 opcode; member 239 __u8 opcode; member 281 __u8 opcode; member 358 __u8 opcode; member 370 __u8 opcode; member 383 __u8 opcode; member 397 __u8 opcode; member 411 __u8 opcode; member 421 __u8 opcode; member 431 __u8 opcode; member [all …]
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| A D | nvme.c | 270 static int nvme_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) in nvme_delete_queue() argument 275 c.delete_queue.opcode = opcode; in nvme_delete_queue() 422 c.create_cq.opcode = nvme_admin_create_cq; in nvme_alloc_cq() 439 c.create_sq.opcode = nvme_admin_create_sq; in nvme_alloc_sq() 459 c.identify.opcode = nvme_admin_identify; in nvme_identify() 491 c.features.opcode = nvme_admin_get_features; in nvme_get_features() 518 c.features.opcode = nvme_admin_set_features; in nvme_set_features() 764 c.rw.opcode = read ? nvme_cmd_read : nvme_cmd_write; in nvme_blk_rw()
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| A D | nvme_apple.c | 50 u8 opcode; member 120 tcb->opcode = cmd->common.opcode; in apple_nvme_submit_cmd()
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| /drivers/mtd/spi/ |
| A D | spi-nor-tiny.c | 75 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) in spi_nor_write_reg() argument 77 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1), in spi_nor_write_reg() 176 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size) in spi_nor_convert_opcode() argument 181 if (table[i][0] == opcode) in spi_nor_convert_opcode() 185 return opcode; in spi_nor_convert_opcode() 188 static inline u8 spi_nor_convert_3to4_read(u8 opcode) in spi_nor_convert_3to4_read() argument 199 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read, in spi_nor_convert_3to4_read() 563 u8 opcode, in spi_nor_set_read_settings() argument 568 read->opcode = opcode; in spi_nor_set_read_settings() 624 nor->read_opcode = read->opcode; in spi_nor_select_read()
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| A D | spi-nor-core.c | 237 return ~op->cmd.opcode; in spi_nor_get_cmd_ext() 240 return op->cmd.opcode; in spi_nor_get_cmd_ext() 286 op->cmd.opcode = (op->cmd.opcode << 8) | ext; in spi_nor_setup_op() 668 return opcode; in spi_nor_convert_opcode() 2328 u8 opcode, in spi_nor_set_read_settings() argument 2333 read->opcode = opcode; in spi_nor_set_read_settings() 2339 u8 opcode, in spi_nor_set_pp_settings() argument 2342 pp->opcode = opcode; in spi_nor_set_pp_settings() 2673 u8 opcode; in spi_nor_parse_bfpt() local 2805 u32 *table, opcode, addr; in spi_nor_parse_profile1() local [all …]
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| A D | sf_dataflash.c | 84 u8 opcode = OP_READ_STATUS; in dataflash_status() local 91 ret = spi_write_then_read(spi, &opcode, 1, NULL, &status, 1); in dataflash_status() 561 u8 opcode = CMD_READ_ID; in jedec_probe() local 572 tmp = spi_write_then_read(spi, &opcode, 1, NULL, id, id_size); in jedec_probe()
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| /drivers/mmc/ |
| A D | iproc_sdhci.c | 179 static int sdhci_iproc_execute_tuning(struct mmc *mmc, u8 opcode) in sdhci_iproc_execute_tuning() argument 190 cmd.cmdidx = opcode; in sdhci_iproc_execute_tuning() 194 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && mmc->bus_width == 8) in sdhci_iproc_execute_tuning() 203 if (opcode == MMC_CMD_SEND_TUNING_BLOCK) in sdhci_iproc_execute_tuning() 221 printf("%s:Tuning failed, opcode = 0x%02x\n", __func__, opcode); in sdhci_iproc_execute_tuning()
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| A D | mtk-sd.c | 472 u32 opcode = cmd->cmdidx; in msdc_cmd_prepare_raw_cmd() local 478 switch (opcode) { in msdc_cmd_prepare_raw_cmd() 512 if (opcode == MMC_CMD_STOP_TRANSMISSION) in msdc_cmd_prepare_raw_cmd() 1246 cmd_err = mmc_send_tuning(mmc, opcode); in msdc_tune_response() 1284 ret = mmc_send_tuning(mmc, opcode); in msdc_tune_data() 1307 ret = mmc_send_tuning(mmc, opcode); in msdc_tune_data() 1369 ret = mmc_send_tuning(mmc, opcode); in msdc_tune_together() 1385 ret = mmc_send_tuning(mmc, opcode); in msdc_tune_together() 1419 ret = msdc_tune_together(dev, opcode); in msdc_execute_tuning() 1443 ret = msdc_tune_response(dev, opcode); in msdc_execute_tuning() [all …]
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| A D | cv1800b_sdhci.c | 35 static int cv1800b_execute_tuning(struct mmc *mmc, u8 opcode) in cv1800b_execute_tuning() argument 48 if (mmc_send_tuning(host->mmc, opcode)) { in cv1800b_execute_tuning()
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| A D | sdhci-cadence.c | 161 unsigned int opcode) in sdhci_cdns_execute_tuning() argument 178 if (WARN_ON(opcode != MMC_CMD_SEND_TUNING_BLOCK_HS200)) in sdhci_cdns_execute_tuning() 183 mmc_send_tuning(mmc, opcode)) { /* bad */ in sdhci_cdns_execute_tuning()
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| A D | mmc-uclass.c | 128 static int dm_mmc_execute_tuning(struct udevice *dev, uint opcode) in dm_mmc_execute_tuning() argument 134 return ops->execute_tuning(dev, opcode); in dm_mmc_execute_tuning() 137 int mmc_execute_tuning(struct mmc *mmc, uint opcode) in mmc_execute_tuning() argument 142 ret = dm_mmc_execute_tuning(mmc->dev, opcode); in mmc_execute_tuning()
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| A D | snps_sdhci.c | 275 static int snps_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) in snps_sdhci_execute_tuning() argument 321 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && mmc->bus_width == 8) in snps_sdhci_execute_tuning() 326 cmd.cmdidx = opcode; in snps_sdhci_execute_tuning()
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| /drivers/ufs/ |
| A D | ufs.c | 1018 enum query_opcode opcode, in ufshcd_init_query() argument 1025 (*request)->upiu_req.opcode = opcode; in ufshcd_init_query() 1045 switch (opcode) { in ufshcd_query_flag() 1064 __func__, opcode); in ufshcd_query_flag() 1087 enum query_opcode opcode, in ufshcd_query_flag_retry() argument 1106 __func__, opcode, idn, ret, retries); in ufshcd_query_flag_retry() 1111 enum query_opcode opcode, in __ufshcd_query_descriptor() argument 1121 __func__, opcode); in __ufshcd_query_descriptor() 1138 switch (opcode) { in __ufshcd_query_descriptor() 1147 __func__, opcode); in __ufshcd_query_descriptor() [all …]
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