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Searched refs:pll (Results 1 – 25 of 50) sorted by relevance

12

/drivers/clk/imx/
A Dclk-pllv3.c53 u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_genericv2_get_rate()
63 u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_genericv2_set_rate()
77 u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_generic_get_rate()
96 val &= ~(pll->div_mask << pll->div_shift); in clk_pllv3_generic_set_rate()
101 while (!(readl(pll->base) & pll->lock_bit)) in clk_pllv3_generic_set_rate()
161 u32 div = readl(pll->base) & pll->div_mask; in clk_pllv3_sys_get_rate()
190 while (!(readl(pll->base) & pll->lock_bit)) in clk_pllv3_sys_set_rate()
209 u32 div = readl(pll->base) & pll->div_mask; in clk_pllv3_av_get_rate()
258 while (!(readl(pll->base) & pll->lock_bit)) in clk_pllv3_av_set_rate()
293 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in imx_clk_pllv3()
[all …]
A Dclk-fracn-gppll.c133 for (i = 0; i < pll->rate_count; i++) in imx_get_pll_settings()
147 for (i = 0; i < pll->rate_count; i++) in clk_fracn_gppll_round_rate()
271 ret = clk_fracn_gppll_wait_lock(pll); in clk_fracn_gppll_set_rate()
306 ret = clk_fracn_gppll_wait_lock(pll); in clk_fracn_gppll_prepare()
341 struct clk_fracn_gppll *pll; in _imx_clk_fracn_gppll() local
345 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in _imx_clk_fracn_gppll()
346 if (!pll) in _imx_clk_fracn_gppll()
349 pll->base = base; in _imx_clk_fracn_gppll()
352 pll->flags = pll_flags; in _imx_clk_fracn_gppll()
354 clk = &pll->clk; in _imx_clk_fracn_gppll()
[all …]
A Dclk-pll14xx.c239 tmp = readl(pll->base); in clk_pll1416x_set_rate()
241 writel(tmp, pll->base); in clk_pll1416x_set_rate()
245 writel(tmp, pll->base); in clk_pll1416x_set_rate()
249 writel(tmp, pll->base); in clk_pll1416x_set_rate()
265 writel(tmp, pll->base); in clk_pll1416x_set_rate()
398 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in imx_clk_pll14xx()
399 if (!pll) in imx_clk_pll14xx()
412 kfree(pll); in imx_clk_pll14xx()
416 pll->base = base; in imx_clk_pll14xx()
421 clk = &pll->clk; in imx_clk_pll14xx()
[all …]
/drivers/clk/at91/
A Dclk-sam9x60-pll.c111 pll->id); in sam9x60_frac_pll_set_rate()
150 pll->id); in sam9x60_frac_pll_get_rate()
175 pll->id); in sam9x60_frac_pll_enable()
234 pll->id); in sam9x60_frac_pll_disable()
265 pll->id); in sam9x60_div_pll_enable()
294 pll->id); in sam9x60_div_pll_disable()
324 pll->id); in sam9x60_div_pll_set_rate()
359 pll->id); in sam9x60_div_pll_get_rate()
405 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in sam9x60_clk_register_pll()
406 if (!pll) in sam9x60_clk_register_pll()
[all …]
/drivers/clk/ti/
A Dclk-k3-pll.c264 clk_pll_16fft_disable_cal(pll); in ti_pll_wait_for_lock()
383 if (!ti_pll_clk_is_bypass(pll)) { in ti_pll_clk_set_rate()
385 ti_pll_clk_bypass(pll, true); in ti_pll_clk_set_rate()
465 clk_pll_16fft_cal_int(pll); in ti_pll_clk_set_rate()
481 ti_pll_clk_bypass(pll, false); in ti_pll_clk_set_rate()
512 struct ti_pll_clk *pll; in clk_register_ti_pll() local
517 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in clk_register_ti_pll()
518 if (!pll) in clk_register_ti_pll()
521 pll->base = reg; in clk_register_ti_pll()
526 kfree(pll); in clk_register_ti_pll()
[all …]
/drivers/clk/starfive/
A Dclk-jh7110-pll.c226 PLLX_SET(pll->offset->pd, pll->offset->pd_mask, PLL_PD_OFF); in jh7110_pll_set_rate()
227 PLLX_SET(pll->offset->dacpd, pll->offset->dacpd_mask, 1); in jh7110_pll_set_rate()
228 PLLX_SET(pll->offset->dsmpd, pll->offset->dsmpd_mask, 1); in jh7110_pll_set_rate()
232 PLLX_SET(pll->offset->pd, pll->offset->pd_mask, PLL_PD_ON); in jh7110_pll_set_rate()
251 dacpd = getbits_le32((ulong)pll->base + pll->offset->dacpd, in jh7110_pllx_recalc_rate()
253 dsmpd = getbits_le32((ulong)pll->base + pll->offset->dsmpd, in jh7110_pllx_recalc_rate()
255 prediv = getbits_le32((ulong)pll->base + pll->offset->prediv, in jh7110_pllx_recalc_rate()
257 fbdiv = getbits_le32((ulong)pll->base + pll->offset->fbdiv, in jh7110_pllx_recalc_rate()
333 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in starfive_jh7110_pll()
334 if (!pll) in starfive_jh7110_pll()
[all …]
/drivers/clk/rockchip/
A Dclk_pll.c314 pll->mode_mask << pll->mode_shift, in rk3036_pll_set_rate()
347 while (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) in rk3036_pll_set_rate()
352 pll->mode_mask << pll->mode_shift, in rk3036_pll_set_rate()
356 pll, readl(base + pll->con_offset), in rk3036_pll_set_rate()
373 shift = pll->mode_shift; in rk3036_pll_get_rate()
461 pll->mode_mask << pll->mode_shift, in rk3588_pll_set_rate()
504 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, in rk3588_pll_set_rate()
548 pll, readl(base + pll->con_offset), in rk3588_pll_set_rate()
564 shift = pll->mode_shift; in rk3588_pll_get_rate()
621 switch (pll->type) { in rockchip_pll_get_rate()
[all …]
A Dclk_rk3036.c51 struct rk3036_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll() local
59 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
65 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
67 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
70 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
75 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkclk_set_pll()
178 struct rk3036_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate() local
200 con = readl(&pll->con0); in rkclk_pll_get_rate()
203 con = readl(&pll->con1); in rkclk_pll_get_rate()
A Dclk_rk3368.c70 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate() local
72 con = readl(&pll->con3); in rkclk_pll_get_rate()
78 con = readl(&pll->con0); in rkclk_pll_get_rate()
81 con = readl(&pll->con1); in rkclk_pll_get_rate()
95 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll() local
104 rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK, in rkclk_set_pll()
107 rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK, in rkclk_set_pll()
110 writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1); in rkclk_set_pll()
120 rk_clrreg(&pll->con3, PLL_RESET_MASK); in rkclk_set_pll()
123 while (!(readl(&pll->con1) & PLL_LOCK_STA)) in rkclk_set_pll()
[all …]
A Dclk_rv1108.c73 struct rv1108_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll() local
80 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
89 rk_clrsetreg(&pll->con3, WORK_MODE_MASK, in rkclk_set_pll()
93 rk_setreg(&pll->con3, 1 << DSMPD_SHIFT); in rkclk_set_pll()
102 rk_clrsetreg(&pll->con2, FRACDIV_MASK, in rkclk_set_pll()
109 while (readl(&pll->con2) & (1 << LOCK_STA_SHIFT)) in rkclk_set_pll()
115 rk_clrsetreg(&pll->con3, WORK_MODE_MASK, in rkclk_set_pll()
127 struct rv1108_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate() local
130 con3 = readl(&pll->con3); in rkclk_pll_get_rate()
133 con0 = readl(&pll->con0); in rkclk_pll_get_rate()
[all …]
A Dclk_rk322x.c49 struct rk322x_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll() local
56 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
62 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
64 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
66 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
69 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
74 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
77 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkclk_set_pll()
180 struct rk322x_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate() local
202 con = readl(&pll->con0); in rkclk_pll_get_rate()
[all …]
A Dclk_rk3128.c44 struct rk3128_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll() local
51 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
57 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
59 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
61 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
64 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
69 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
72 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkclk_set_pll()
246 struct rk3128_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate() local
267 con = readl(&pll->con0); in rkclk_pll_get_rate()
[all …]
/drivers/clk/adi/
A Dclk-adi-pll.c42 u32 m = ((reg & pll->mask) >> pll->shift) + pll->m_offset; in sc5xx_cgu_pll_get_rate()
45 m = pll->max; in sc5xx_cgu_pll_get_rate()
47 if (pll->half_m) in sc5xx_cgu_pll_get_rate()
65 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in sc5xx_cgu_pll()
66 if (!pll) in sc5xx_cgu_pll()
69 pll->base = base; in sc5xx_cgu_pll()
70 pll->shift = shift; in sc5xx_cgu_pll()
72 pll->max = pll->mask + 1; in sc5xx_cgu_pll()
74 pll->half_m = half_m; in sc5xx_cgu_pll()
76 clk = &pll->clk; in sc5xx_cgu_pll()
[all …]
/drivers/clk/sophgo/
A Dclk-pll.c42 cv1800b_clk_clrbit(pll->base, &pll->pll_pwd); in cv1800b_ipll_enable()
50 cv1800b_clk_setbit(pll->base, &pll->pll_pwd); in cv1800b_ipll_disable()
59 u32 reg = readl(pll->base + pll->pll_reg); in cv1800b_ipll_get_rate()
140 if (!cv1800b_clk_getbit(pll->ipll.base, &pll->syn.en)) in cv1800b_fpll_get_rate()
143 syn_set = readl(pll->ipll.base + pll->syn.set); in cv1800b_fpll_get_rate()
147 val = readl(pll->ipll.base + pll->ipll.pll_reg); in cv1800b_fpll_get_rate()
152 if (cv1800b_clk_getbit(pll->ipll.base, &pll->syn.clk_half)) in cv1800b_fpll_get_rate()
202 if (!cv1800b_clk_getbit(pll->ipll.base, &pll->syn.en)) in cv1800b_fpll_set_rate()
241 writel(syn_sel, pll->ipll.base + pll->syn.set); in cv1800b_fpll_set_rate()
255 cv1800b_clk_setbit(pll->ipll.base, &pll->syn.en); in cv1800b_fpll_set_parent()
[all …]
/drivers/clk/mediatek/
A Dclk-mtk.c179 ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS; in __mtk_pll_recalc_rate()
215 if (pll->pd_reg != pll->pcw_reg) { in mtk_pll_set_rate_regs()
221 val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift); in mtk_pll_set_rate_regs()
224 if (pll->pcw_chg_reg) { in mtk_pll_set_rate_regs()
255 fmin = pll->fmin ? pll->fmin : 1000 * MHZ; in mtk_pll_calc_values()
257 if (freq > pll->fmax) in mtk_pll_calc_values()
258 freq = pll->fmax; in mtk_pll_calc_values()
267 ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS; in mtk_pll_calc_values()
307 postdiv = (readl(priv->base + pll->pd_reg) >> pll->pd_shift) & in mtk_apmixedsys_get_rate()
311 pcw = readl(priv->base + pll->pcw_reg) >> pll->pcw_shift; in mtk_apmixedsys_get_rate()
[all …]
/drivers/clk/exynos/
A Dclk-pll.c49 pll_con3 = readl_relaxed(pll->con_reg); in samsung_pll0822x_recalc_rate()
83 pll_con3 = readl_relaxed(pll->con_reg); in samsung_pll0831x_recalc_rate()
84 pll_con5 = readl_relaxed(pll->con_reg + 8); in samsung_pll0831x_recalc_rate()
104 struct samsung_clk_pll *pll; in _samsung_clk_register_pll() local
109 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in _samsung_clk_register_pll()
110 if (!pll) in _samsung_clk_register_pll()
113 pll->con_reg = base + pll_clk->con_offset; in _samsung_clk_register_pll()
114 pll->type = pll_clk->type; in _samsung_clk_register_pll()
115 clk = &pll->clk; in _samsung_clk_register_pll()
126 kfree(pll); in _samsung_clk_register_pll()
[all …]
/drivers/video/sunxi/
A Dsunxi_dw_hdmi.c39 u32 pll; member
102 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_init()
110 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_init()
134 writel(0x30dc5fc0, &phy->pll); in sunxi_dw_hdmi_phy_set()
145 setbits_le32(&phy->pll, 0x3f); in sunxi_dw_hdmi_phy_set()
152 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
160 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()
166 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
174 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()
180 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
[all …]
/drivers/clk/
A Dclk_zynqmp.c427 enum zynqmp_clk pll; in zynqmp_clk_get_cpu_rate() local
440 pll = pll_src[ACPU_CLK_SRC][srcsel]; in zynqmp_clk_get_cpu_rate()
451 enum zynqmp_clk pll; in zynqmp_clk_get_ddr_rate() local
464 pll = pll_src[DDR_CLK_SRC][srcsel]; in zynqmp_clk_get_ddr_rate()
475 enum zynqmp_clk pll; in zynqmp_clk_get_dll_rate() local
486 pll = pll_src[DLL_CLK_SRC][srcsel]; in zynqmp_clk_get_dll_rate()
497 enum zynqmp_clk pll; in zynqmp_clk_get_peripheral_rate() local
537 enum zynqmp_clk pll; in zynqmp_clk_get_crf_crl_rate() local
602 if (pll == iopll_to_fpd) in zynqmp_clk_get_crf_crl_rate()
603 pll = iopll; in zynqmp_clk_get_crf_crl_rate()
[all …]
A Dclk_k210.c320 u8 pll; member
354 .pll = (_pll), \
370 .pll = 2,
888 reg = readl(priv->base + pll->off); in k210_pll_set_rate()
897 writel(reg, priv->base + pll->off); in k210_pll_set_rate()
938 u32 mask = (BIT(pll->width) - 1) << pll->shift; in k210_pll_waitfor_lock()
967 writel(reg, priv->base + pll->off); in k210_pll_enable()
971 writel(reg, priv->base + pll->off); in k210_pll_enable()
973 writel(reg, priv->base + pll->off); in k210_pll_enable()
977 writel(reg, priv->base + pll->off); in k210_pll_enable()
[all …]
A Dclk_sandbox_ccf.c58 struct clk_pllv3 *pll; in sandbox_clk_pllv3() local
63 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in sandbox_clk_pllv3()
64 if (!pll) in sandbox_clk_pllv3()
67 pll->div_mask = div_mask; in sandbox_clk_pllv3()
68 clk = &pll->clk; in sandbox_clk_pllv3()
72 kfree(pll); in sandbox_clk_pllv3()
/drivers/usb/host/
A Dehci-mxs.c27 struct mxs_register_32 *pll; member
43 writel(port->pll_en_bits, (u32)port->pll + pll_offset); in ehci_mxs_toggle_clock()
47 writel(port->pll_dis_bits, (u32)port->pll + pll_offset); in ehci_mxs_toggle_clock()
190 port->pll = (struct mxs_register_32 *)clk_reg; in ehci_usb_ofdata_to_platdata()
194 port->pll = PLL0CTRL0(port->pll); in ehci_usb_ofdata_to_platdata()
197 port->pll = PLL1CTRL0(port->pll); in ehci_usb_ofdata_to_platdata()
199 debug("%s: pll_reg: 0x%p clk_id: %d\n", __func__, port->pll, clk_id); in ehci_usb_ofdata_to_platdata()
/drivers/clk/nuvoton/
A Dclk_npcm.c42 struct npcm_clk_pll *pll = clk_data->clk_plls; in npcm_clk_pll_get() local
46 if (pll->id == id) in npcm_clk_pll_get()
47 return pll; in npcm_clk_pll_get()
48 pll++; in npcm_clk_pll_get()
193 struct npcm_clk_pll *pll; in npcm_clk_get_pll_fout() local
200 pll = npcm_clk_pll_get(priv->clk_data, clk->id); in npcm_clk_get_pll_fout()
201 if (!pll) in npcm_clk_get_pll_fout()
204 parent.id = pll->parent_id; in npcm_clk_get_pll_fout()
211 val = readl(priv->base + pll->reg); in npcm_clk_get_pll_fout()
219 if (pll->flags & POST_DIV2) in npcm_clk_get_pll_fout()
/drivers/video/
A Di915_reg.h168 #define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) argument
175 #define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0) argument
176 #define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1) argument
/drivers/clk/stm32/
A Dclk-stm32mp1.c900 const struct stm32mp1_clk_pll *pll = priv->data->pll; in pll_get_fref_ck() local
923 const struct stm32mp1_clk_pll *pll = priv->data->pll; in pll_get_fvco() local
957 const struct stm32mp1_clk_pll *pll = priv->data->pll; in stm32mp1_read_pll_freq() local
1585 const struct stm32mp1_clk_pll *pll = priv->data->pll; in pll_start() local
1595 const struct stm32mp1_clk_pll *pll = priv->data->pll; in pll_output() local
1617 const struct stm32mp1_clk_pll *pll = priv->data->pll; in pll_stop() local
1636 const struct stm32mp1_clk_pll *pll = priv->data->pll; in pll_config_output() local
1652 const struct stm32mp1_clk_pll *pll = priv->data->pll; in pll_config() local
1698 const struct stm32mp1_clk_pll *pll = priv->data->pll; in pll_csg() local
1722 const struct stm32mp1_clk_pll *pll = priv->data->pll; in pll_set_rate() local
[all …]
/drivers/clk/altera/
A Dclk-agilex.c132 if (pll == MEMBUS_MAINPLL) in membus_wait_for_req()
138 if (pll == MEMBUS_MAINPLL) in membus_wait_for_req()
151 static int membus_write_pll(struct socfpga_clk_plat *plat, u32 pll, in membus_write_pll() argument
162 if (pll == MEMBUS_MAINPLL) in membus_write_pll()
169 return membus_wait_for_req(plat, pll, timeout); in membus_write_pll()
172 static int membus_read_pll(struct socfpga_clk_plat *plat, u32 pll, in membus_read_pll() argument
182 if (pll == MEMBUS_MAINPLL) in membus_read_pll()
189 if (membus_wait_for_req(plat, pll, timeout)) in membus_read_pll()
192 if (pll == MEMBUS_MAINPLL) in membus_read_pll()
208 membus_read_pll(plat, pll, membus_pll[i].reg, in membus_pll_configs()
[all …]

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