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Searched refs:pll_con3 (Results 1 – 1 of 1) sorted by relevance

/drivers/clk/exynos/
A Dclk-pll.c46 u32 mdiv, pdiv, sdiv, pll_con3; in samsung_pll0822x_recalc_rate() local
49 pll_con3 = readl_relaxed(pll->con_reg); in samsung_pll0822x_recalc_rate()
50 mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK; in samsung_pll0822x_recalc_rate()
51 pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK; in samsung_pll0822x_recalc_rate()
52 sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK; in samsung_pll0822x_recalc_rate()
79 u32 mdiv, pdiv, sdiv, pll_con3, pll_con5; in samsung_pll0831x_recalc_rate() local
83 pll_con3 = readl_relaxed(pll->con_reg); in samsung_pll0831x_recalc_rate()
85 mdiv = (pll_con3 >> PLL0831X_MDIV_SHIFT) & PLL0831X_MDIV_MASK; in samsung_pll0831x_recalc_rate()
86 pdiv = (pll_con3 >> PLL0831X_PDIV_SHIFT) & PLL0831X_PDIV_MASK; in samsung_pll0831x_recalc_rate()
87 sdiv = (pll_con3 >> PLL0831X_SDIV_SHIFT) & PLL0831X_SDIV_MASK; in samsung_pll0831x_recalc_rate()

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