| /dts/upstream/Bindings/display/ |
| A D | mipi-dsi-bus.txt | 1 MIPI DSI (Display Serial Interface) busses
9 standard properties in the context of the DSI bus.
11 Each DSI host provides a DSI bus. The DSI host controller's node contains a
18 DSI host
22 a DSI host, the following properties apply to a node representing a DSI host.
39 DSI peripheral
72 Peripherals that support dual channel DSI
80 an input endpoint of the DSI peripheral.
87 - (1), (2) and (3) are examples of a DSI host and peripheral on the DSI bus
90 DSI host using of-graph bindings.
[all …]
|
| A D | brcm,bcm2835-dsi0.yaml | 7 title: Broadcom VC4 (VideoCore4) DSI Controller
30 - description: The DSI PLL clock feeding the DSI analog PHY
31 - description: The DSI ESC clock
32 - description: The DSI pixel clock
43 # - description: The DSI byte clock for the PHY
44 # - description: The DSI DDR2 clock
45 # - description: The DSI DDR clock
|
| A D | dsi-controller.yaml | 7 title: Common Properties for DSI Display Panels
13 This document defines device tree properties common to DSI, Display
22 Notice: this binding concerns DSI panels connected directly to a master
23 without any intermediate port graph to the panel. Each DSI master
37 another DSI host to drive the same peripheral. Hardware supporting
39 to be driven by the same clock. Only the DSI host instance
50 description: Panels connected to the DSI link
58 The virtual channel number of a DSI peripheral. Must be in the range
59 from 0 to 3, as DSI uses a 2-bit addressing scheme. Some DSI
|
| A D | st,stm32-dsi.yaml | 7 title: STMicroelectronics STM32 DSI host controller
14 The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
29 - description: DSI bus clock
58 DSI input port node, connected to the ltdc rgb output port.
64 DSI output port node, connected to a panel or a bridge input port.
|
| /dts/upstream/Bindings/clock/ |
| A D | qcom,mmcc.yaml | 86 - description: DSI phy instance 1 dsi clock
87 - description: DSI phy instance 1 byte clock
88 - description: DSI phy instance 2 dsi clock
89 - description: DSI phy instance 2 byte clock
121 - description: DSI phy instance 0 dsi clock
122 - description: DSI phy instance 0 byte clock
149 - description: DSI phy instance 0 dsi clock
150 - description: DSI phy instance 0 byte clock
151 - description: DSI phy instance 1 dsi clock
188 - description: DSI phy instance 0 dsi clock
[all …]
|
| A D | qcom,dispcc-sc8280xp.yaml | 38 - description: DSI 0 PLL byte clock
39 - description: DSI 0 PLL DSI clock
40 - description: DSI 1 PLL byte clock
41 - description: DSI 1 PLL DSI clock
|
| A D | qcom,gcc-msm8953.yaml | 27 - description: Byte clock from DSI PHY0
28 - description: Pixel clock from DSI PHY0
29 - description: Byte clock from DSI PHY1
30 - description: Pixel clock from DSI PHY1
|
| /dts/upstream/Bindings/display/panel/ |
| A D | sharp,lq101r1sx01.yaml | 13 This panel requires a dual-channel DSI host to operate. It supports two modes:
17 Each of the DSI channels controls a separate DSI peripheral. The peripheral
18 driven by the first link (DSI-LINK1), left or even, is considered the primary
20 to the peripheral driven by the second link (DSI-LINK2, right or odd).
22 Note that in video mode the DSI-LINK1 interface always provides the left/even
23 pixels and DSI-LINK2 always provides the right/odd pixels. In command mode it
49 phandle to the DSI peripheral on the secondary link. Note that the
50 presence of this property marks the containing node as DSI-LINK1
|
| A D | jdi,lpm102a188a.yaml | 7 title: JDI LPM102A188A 2560x1800 10.2" DSI Panel
13 This panel requires a dual-channel DSI host to operate. It supports two modes:
17 Each of the DSI channels controls a separate DSI peripheral. The peripheral
18 driven by the first link (DSI-LINK1) is considered the primary peripheral
20 peripheral driven by the second link (DSI-LINK2).
43 phandle to the DSI peripheral on the secondary link. Note that the
44 presence of this property marks the containing node as DSI-LINK1.
|
| A D | truly,nt35597-2K-display.yaml | 7 title: Truly NT35597 DSI 2K display
13 Truly NT35597 DSI 2K display is used on the Qualcomm SDM845 MTP board.
38 Gpio for choosing the mode of the display for single DSI or Dual DSI.
39 This should be low for dual DSI and high for single DSI mode.
|
| A D | orisetech,otm8009a.yaml | 7 title: Orise Tech OTM8009A 3.97" 480x800 TFT LCD panel (MIPI-DSI video mode)
14 a MIPI-DSI video interface. Its backlight is managed through the DSI link.
25 description: DSI virtual channel
|
| A D | raspberrypi,7inch-touchscreen.yaml | 14 This DSI panel contains:
16 - TC358762 DSI->DPI bridge
17 - Atmel microcontroller on I2C for power sequencing the DSI bridge and
21 and this binding covers the DSI display parts but not its touch input.
|
| /dts/upstream/Bindings/display/bridge/ |
| A D | renesas,dsi.yaml | 7 title: Renesas RZ/G2L MIPI DSI Encoder
36 - description: DSI Packet Receive interrupt
37 - description: DSI Fatal Error interrupt
38 - description: DSI D-PHY PPI interrupt
53 - description: DSI D-PHY PLL multiplied clock
54 - description: DSI D-PHY system clock
55 - description: DSI AXI bus clock
56 - description: DSI Register access clock
57 - description: DSI Video clock
58 - description: DSI D-PHY Escape mode transmit clock
[all …]
|
| A D | intel,keembay-dsi.yaml | 27 - description: MIPI DSI clock
28 - description: MIPI DSI econfig clock
29 - description: MIPI DSI config clock
43 description: MIPI DSI input port.
47 description: DSI output port.
|
| A D | chipone,icn6211.yaml | 7 title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge
13 ICN6211 is MIPI-DSI to RGB Converter bridge from chipone.
15 It has a flexible configuration of MIPI DSI signal input and
25 description: virtual channel number of a DSI peripheral
56 Video port for MIPI DSI input
65 description: array of physical DSI data lane indexes.
|
| A D | lontium,lt9211.yaml | 7 title: Lontium LT9211 DSI/LVDS/DPI to DSI/LVDS/DPI bridge.
13 The LT9211 are bridge devices which convert Single/Dual-Link DSI/LVDS
14 or Single DPI to Single/Dual-Link DSI/LVDS or Single DPI.
41 Primary MIPI DSI port-1 for MIPI input or
54 Primary MIPI DSI port-1 for MIPI output or
|
| A D | toshiba,tc358762.yaml | 7 title: Toshiba TC358762 MIPI DSI to MIPI DPI bridge
13 The TC358762 is bridge device which converts MIPI DSI to MIPI DPI.
22 description: virtual channel number of a DSI peripheral
37 Video port for MIPI DSI input
|
| A D | ti,dlpc3433.yaml | 7 title: TI DLPC3433 MIPI DSI to DMD bridge
14 TI DLPC3433 is a MIPI DSI based display controller bridge
17 It has a flexible configuration of MIPI DSI and DPI signal
49 description: Video port for MIPI DSI input.
58 description: array of physical DSI data lane indexes.
|
| A D | ti,sn65dsi83.yaml | 7 title: SN65DSI83 and SN65DSI84 DSI to LVDS bridge chip
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
48 description: Video port for MIPI DSI Channel-A input
57 description: array of physical DSI data lane indexes.
68 description: Video port for MIPI DSI Channel-B input
77 description: array of physical DSI data lane indexes.
|
| A D | renesas,dsi-csi2-tx.yaml | 7 title: Renesas R-Car MIPI DSI/CSI-2 Encoder
13 This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
14 R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up
30 - description: DSI (and CSI-2) functional clock
56 description: DSI/CSI-2 output port
|
| /dts/upstream/Bindings/display/ti/ |
| A D | ti,omap5-dss.txt | 21 - DSS Submodules: RFBI, DSI, HDMI
59 DSI
66 - interrupts: the DSI interrupt line
68 - vdd-supply: power supply for DSI
73 - Video port for DSI output
74 - DSI controlled peripherals
76 DSI Endpoint required properties:
77 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
|
| A D | ti,omap4-dss.txt | 21 - DSS Submodules: RFBI, VENC, DSI, HDMI
78 DSI
85 - interrupts: the DSI interrupt line
87 - vdd-supply: power supply for DSI
92 - Video port for DSI output
93 - DSI controlled peripherals
95 DSI Endpoint required properties:
96 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
|
| A D | ti,omap3-dss.txt | 72 DSI
79 - interrupts: the DSI interrupt line
81 - vdd-supply: power supply for DSI
85 DSI Endpoint required properties:
86 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
|
| /dts/upstream/Bindings/display/mediatek/ |
| A D | mediatek,dsi.yaml | 7 title: MediaTek DSI Controller
15 The MediaTek DSI function block is a sink of the display subsystem and can
16 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
78 port of an attached DSI panel or DSI-to-eDP encoder chip.
89 description: DSI input port, usually from DITHER, DSC or MERGE
94 DSI output to an attached DSI panel, or a DSI-to-X encoder chip
|
| /dts/upstream/Bindings/phy/ |
| A D | mixel,mipi-dsi-phy.yaml | 7 title: Mixel DSI PHY for i.MX8
13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
15 electrical signals for DSI.
18 in either MIPI-DSI PHY mode or LVDS PHY mode.
|