1menu "Functionality shared between NXP SoCs"
2
3config FSL_TRUST_ARCH_v1
4	bool
5
6config NXP_ESBC
7	bool "NXP ESBC (secure boot) functionality"
8	select FSL_TRUST_ARCH_v1 if ARCH_P3041 || ARCH_P4080 || \
9		ARCH_P5040 || ARCH_P2041
10	help
11	  Enable Freescale Secure Boot feature. Normally selected by defconfig.
12	  If unsure, do not change.
13
14menu "Chain of trust / secure boot options"
15	depends on !FIT_SIGNATURE && NXP_ESBC
16
17config CHAIN_OF_TRUST
18	select FSL_CAAM
19	select ARCH_MISC_INIT
20	select FSL_ISBC_KEY_EXT if (ARM || FSL_CORENET) && !SYS_RAMBOOT
21	select FSL_SEC_MON
22	select SPL_BOARD_INIT if (ARM && SPL)
23	select SPL_HASH if (ARM && SPL)
24	select SHA_HW_ACCEL
25	select SHA_PROG_HW_ACCEL
26	select ENV_IS_NOWHERE
27	select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
28	select CMD_EXT4 if ARM
29	select CMD_EXT4_WRITE if ARM
30	imply CMD_BLOB
31	imply CMD_HASH if ARM
32	def_bool y
33
34config CMD_ESBC_VALIDATE
35	bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
36	default y
37	help
38	  This option enables two commands used for secure booting:
39
40	    esbc_validate - validate signature using RSA verification
41	    esbc_halt - put the core in spin loop (Secure Boot Only)
42
43config ESBC_HDR_LS
44	bool
45
46config ESBC_ADDR_64BIT
47	def_bool y
48	depends on FSL_LAYERSCAPE
49	help
50	  For Layerscape based platforms, ESBC image Address in Header is 64bit.
51
52config FSL_ISBC_KEY_EXT
53	bool
54	help
55	  The key used for verification of next level images is picked up from
56	  an Extension Table which has been verified by the ISBC (Internal
57	  Secure boot Code) in boot ROM of the SoC.  The feature is only
58	  applicable in case of NOR boot and is not applicable in case of
59	  RAMBOOT (NAND, SD, SPI).  For Layerscape, this feature is available
60	  for all device if IE Table is copied to XIP memory Also, for
61	  Layerscape, ISBC doesn't verify this table.
62
63config SYS_FSL_SFP_BE
64	def_bool y
65	depends on PPC || FSL_LSCH2 || ARCH_LS1021A
66
67config SYS_FSL_SFP_LE
68	def_bool y
69	depends on !SYS_FSL_SFP_BE
70
71choice
72	prompt "SFP IP revision"
73	default SYS_FSL_SFP_VER_3_0 if PPC
74	default SYS_FSL_SFP_VER_3_4
75
76config SYS_FSL_SFP_VER_3_0
77	bool "SFP version 3.0"
78
79config SYS_FSL_SFP_VER_3_2
80	bool "SFP version 3.2"
81
82config SYS_FSL_SFP_VER_3_4
83	bool "SFP version 3.4"
84
85endchoice
86
87config FSL_SEC_MON
88	bool
89	help
90	  Freescale Security Monitor block is responsible for monitoring
91	  system states.
92	  Security Monitor can be transitioned on any security failures,
93	  like software violations or hardware security violations.
94
95choice
96	prompt "Security monitor interaction endianess"
97	depends on FSL_SEC_MON
98	default SYS_FSL_SEC_MON_BE if PPC
99	default SYS_FSL_SEC_MON_LE
100
101config SYS_FSL_SEC_MON_LE
102	bool "Security monitor interactions are little endian"
103
104config SYS_FSL_SEC_MON_BE
105	bool "Security monitor interactions are big endian"
106
107endchoice
108
109config SPL_UBOOT_KEY_HASH
110	string "Non-SRK key hash for U-Boot public/private key pair"
111	depends on SPL
112	default ""
113	help
114	  Set the key hash for U-Boot here if public/private key pair used to
115	  sign U-Boot are different from the SRK hash put in the fuse.  Example
116	  of a key hash is
117	  41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
118	  Otherwise leave this empty.
119
120if PPC
121
122config BOOTSCRIPT_COPY_RAM
123	bool "Secure boot copies boot script to RAM"
124	help
125	  On systems that support chain of trust booting, a number of addresses
126	  are required to set variables that are used in the copying and then
127	  verification of different parts of the system.  If enabled, the subsequent
128	  options are for what location to use in each step.
129
130config BS_ADDR_DEVICE
131	hex "Address in RAM for bs_device"
132	depends on BOOTSCRIPT_COPY_RAM
133
134config BS_SIZE
135	hex "The size of bs_size which is the amount read from bs_device"
136	depends on BOOTSCRIPT_COPY_RAM
137
138config BS_ADDR_RAM
139	hex "Address in RAM for bs_ram"
140	depends on BOOTSCRIPT_COPY_RAM
141
142config BS_HDR_ADDR_DEVICE
143	hex "Address in RAM for bs_hdr_device"
144	depends on BOOTSCRIPT_COPY_RAM
145
146config BS_HDR_SIZE
147	hex "The size of bs_hdr_size which is the amount read from bs_hdr_device"
148	depends on BOOTSCRIPT_COPY_RAM
149
150config BS_HDR_ADDR_RAM
151	hex "Address in RAM for bs_hdr_ram"
152	depends on BOOTSCRIPT_COPY_RAM
153
154config BOOTSCRIPT_HDR_ADDR
155	hex "CONFIG_BOOTSCRIPT_HDR_ADDR"
156	default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM
157
158endif
159
160config SYS_FSL_SRK_LE
161	def_bool y
162	depends on ARM
163
164config KEY_REVOCATION
165	def_bool y
166
167endmenu
168
169config DEEP_SLEEP
170	bool "Enable SoC deep sleep feature"
171	depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
172	default y
173	help
174	  Indicates this SoC supports deep sleep feature. If deep sleep is
175	  supported, core will start to execute uboot when wakes up.
176
177config LAYERSCAPE_NS_ACCESS
178	bool "Layerscape non-secure access support"
179	depends on ARCH_LS1021A || FSL_LSCH2
180
181config PCIE1
182	bool "PCIe controller #1"
183	depends on LAYERSCAPE_NS_ACCESS || PPC
184
185config PCIE2
186	bool "PCIe controller #2"
187	depends on LAYERSCAPE_NS_ACCESS || PPC
188
189config PCIE3
190	bool "PCIe controller #3"
191	depends on LAYERSCAPE_NS_ACCESS || PPC
192
193config PCIE4
194	bool "PCIe controller #4"
195	depends on LAYERSCAPE_NS_ACCESS || PPC
196
197config FSL_USE_PCA9547_MUX
198	bool "Enable PCA9547 I2C Mux on Freescale boards"
199	depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
200	help
201	 This option enables the PCA9547 I2C mux on Freescale boards.
202
203config VID
204	bool "Enable Freescale VID"
205	depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (I2C || DM_I2C)
206	help
207	 This option enables setting core voltage based on individual
208	 values saved in SoC fuses.
209
210config SPL_VID
211	bool "Enable Freescale VID in SPL"
212	depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (SPL_I2C || DM_SPL_I2C)
213	help
214	 This option enables setting core voltage based on individual
215	 values saved in SoC fuses, in SPL.
216
217if VID || SPL_VID
218
219config VID_FLS_ENV
220	string "Environment variable for overriding VDD"
221	help
222	  This option allows for specifying the environment variable
223	  to check to override VDD information.
224
225config VOL_MONITOR_INA220
226	bool "Enable the INA220 voltage monitor read"
227	help
228	  This option enables INA220 voltage monitor read
229	  functionality. It is used by the common VID driver.
230
231config VOL_MONITOR_IR36021_READ
232	bool "Enable the IR36021 voltage monitor read"
233	help
234	 This option enables IR36021 voltage monitor read
235	 functionality. It is used by the common VID driver.
236
237config VOL_MONITOR_IR36021_SET
238	bool "Enable the IR36021 voltage monitor set"
239	help
240	 This option enables IR36021 voltage monitor set
241	 functionality. It is used by the common VID driver.
242
243config VOL_MONITOR_LTC3882_READ
244	bool "Enable the LTC3882 voltage monitor read"
245	help
246	 This option enables LTC3882 voltage monitor read
247	 functionality. It is used by the common VID driver.
248
249config VOL_MONITOR_LTC3882_SET
250	bool "Enable the LTC3882 voltage monitor set"
251	help
252	 This option enables LTC3882 voltage monitor set
253	 functionality. It is used by the common VID driver.
254
255config VOL_MONITOR_ISL68233_READ
256	bool "Enable the ISL68233 voltage monitor read"
257	help
258	 This option enables ISL68233 voltage monitor read
259	 functionality. It is used by the common VID driver.
260
261config VOL_MONITOR_ISL68233_SET
262	bool "Enable the ISL68233 voltage monitor set"
263	help
264	 This option enables ISL68233 voltage monitor set
265	 functionality. It is used by the common VID driver.
266
267endif
268
269config SYS_FSL_NUM_CC_PLLS
270	int "Number of clock control PLLs"
271	depends on MPC85xx || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A
272	default 2 if ARCH_LS1021A || ARCH_LS1028A || FSL_LSCH2
273	default 6 if FSL_LSCH3 || MPC85xx
274
275config SYS_FSL_ESDHC_BE
276	bool
277
278config SYS_FSL_IFC_BE
279	bool
280
281config SYS_FSL_IFC_BANK_COUNT
282	int "Maximum banks of Integrated flash controller"
283	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || \
284		ARCH_LS1088A || ARCH_LS1021A || ARCH_B4860 || ARCH_B4420 || \
285		ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || \
286		ARCH_T2080 || ARCH_C29X || ARCH_P1010 || ARCH_BSC9131 || \
287		ARCH_BSC9132
288	default 3 if ARCH_BSC9131 || ARCH_BSC9132
289	default 4 if ARCH_LS1043A || ARCH_LS1046A || ARCH_B4860 || \
290			ARCH_B4420 || ARCH_P1010
291	default 8 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LS1021A || \
292			ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || \
293			ARCH_T1024 || ARCH_T2080 || ARCH_C29X
294
295config FSL_QIXIS
296	bool "Enable QIXIS support"
297	depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
298
299config QIXIS_I2C_ACCESS
300	bool "Access to QIXIS is over i2c"
301	depends on FSL_QIXIS
302	default y
303
304config HAS_FSL_DR_USB
305	def_bool y
306	depends on USB_EHCI_HCD && PPC
307
308config SYS_DPAA_FMAN
309	bool
310
311config SYS_FSL_SRDS_1
312	bool
313
314config SYS_FSL_SRDS_2
315	bool
316
317config SYS_HAS_SERDES
318	bool
319
320endmenu
321