1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. 4 */ 5 6 #ifndef _ASM_ARC_ARCREGS_H 7 #define _ASM_ARC_ARCREGS_H 8 9 #include <asm/cache.h> 10 11 /* 12 * ARC architecture has additional address space - auxiliary registers. 13 * These registers are mostly used for configuration purposes. 14 * These registers are not memory mapped and special commands are used for 15 * access: "lr"/"sr". 16 */ 17 18 /* 19 * Typically 8 least significant bits of Build Configuration Register (BCR) 20 * describe version of the HW block in question. Moreover if decoded version 21 * is 0 this means given HW block is absent - this is especially useful because 22 * we may safely read BRC regardless HW block existence while an attempt to 23 * access any other AUX regs associated with this HW block lead to imediate 24 * "instruction error" exception. 25 * 26 * I.e. before using any cofigurable HW block it's required to make sure it 27 * exists at all, and for that we introduce a special macro below. 28 */ 29 #define ARC_BCR_VERSION_MASK GENMASK(7, 0) 30 #define ARC_FEATURE_EXISTS(bcr) !!(__builtin_arc_lr(bcr) & ARC_BCR_VERSION_MASK) 31 32 #define ARC_AUX_IDENTITY 0x04 33 #define ARC_AUX_STATUS32 0x0a 34 35 /* STATUS32 Bits Positions */ 36 #define STATUS_AD_BIT 19 /* Enable unaligned access */ 37 38 /* Instruction cache related auxiliary registers */ 39 #define ARC_AUX_IC_IVIC 0x10 40 #define ARC_AUX_IC_CTRL 0x11 41 #define ARC_AUX_IC_IVIL 0x19 42 #if (CONFIG_ARC_MMU_VER == 3) 43 #define ARC_AUX_IC_PTAG 0x1E 44 #endif 45 #define ARC_BCR_IC_BUILD 0x77 46 #define AUX_AUX_CACHE_LIMIT 0x5D 47 #define ARC_AUX_NON_VOLATILE_LIMIT 0x5E 48 49 /* ICCM and DCCM auxiliary registers */ 50 #define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */ 51 #define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */ 52 53 /* CSM auxiliary registers */ 54 #define ARC_AUX_CSM_ENABLE 0x9A0 55 56 /* Timer related auxiliary registers */ 57 #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ 58 #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */ 59 #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */ 60 61 #define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */ 62 #define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */ 63 #define ARC_AUX_TIMER1_LIMIT 0x102 /* Timer 1 limit */ 64 65 #define ARC_AUX_INTR_VEC_BASE 0x25 66 67 /* Data cache related auxiliary registers */ 68 #define ARC_AUX_DC_IVDC 0x47 69 #define ARC_AUX_DC_CTRL 0x48 70 71 #define ARC_AUX_DC_IVDL 0x4A 72 #define ARC_AUX_DC_FLSH 0x4B 73 #define ARC_AUX_DC_FLDL 0x4C 74 #if (CONFIG_ARC_MMU_VER == 3) 75 #define ARC_AUX_DC_PTAG 0x5C 76 #endif 77 #define ARC_BCR_DC_BUILD 0x72 78 #define ARC_BCR_SLC 0xce 79 #define ARC_AUX_SLC_CONFIG 0x901 80 #define ARC_AUX_SLC_CTRL 0x903 81 #define ARC_AUX_SLC_FLUSH 0x904 82 #define ARC_AUX_SLC_INVALIDATE 0x905 83 #define ARC_AUX_SLC_IVDL 0x910 84 #define ARC_AUX_SLC_FLDL 0x912 85 #define ARC_AUX_SLC_RGN_START 0x914 86 #define ARC_AUX_SLC_RGN_START1 0x915 87 #define ARC_AUX_SLC_RGN_END 0x916 88 #define ARC_AUX_SLC_RGN_END1 0x917 89 #define ARC_BCR_CLUSTER 0xcf 90 91 /* MMU Management regs */ 92 #define ARC_AUX_MMU_BCR 0x6f 93 94 /* IO coherency related auxiliary registers */ 95 #define ARC_AUX_IO_COH_ENABLE 0x500 96 #define ARC_AUX_IO_COH_PARTIAL 0x501 97 #define ARC_AUX_IO_COH_AP0_BASE 0x508 98 #define ARC_AUX_IO_COH_AP0_SIZE 0x509 99 100 /* XY-memory related */ 101 #define ARC_AUX_XY_BUILD 0x79 102 103 /* DSP-extensions related auxiliary registers */ 104 #define ARC_AUX_DSP_BUILD 0x7A 105 #define ARC_AUX_DSP_CTRL 0x59F 106 107 /* ARC Subsystems related auxiliary registers */ 108 #define ARC_AUX_SUBSYS_BUILD 0xF0 109 110 #ifndef __ASSEMBLY__ 111 #include <linux/bitops.h> 112 113 /* Accessors for auxiliary registers */ 114 #define read_aux_reg(reg) __builtin_arc_lr(reg) 115 116 /* gcc builtin sr needs reg param to be long immediate */ 117 #define write_aux_reg(reg_immed, val) \ 118 __builtin_arc_sr((unsigned int)val, reg_immed) 119 120 /* ARCNUM [15:8] - field to identify each core in a multi-core system */ 121 #define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8) 122 is_isa_arcv2(void)123static const inline int is_isa_arcv2(void) 124 { 125 return IS_ENABLED(CONFIG_ISA_ARCV2); 126 } 127 is_isa_arcompact(void)128static const inline int is_isa_arcompact(void) 129 { 130 return IS_ENABLED(CONFIG_ISA_ARCOMPACT); 131 } 132 #endif /* __ASSEMBLY__ */ 133 134 #endif /* _ASM_ARC_ARCREGS_H */ 135