1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
4  */
5 
6 #ifndef __ASM_ARC_CACHE_H
7 #define __ASM_ARC_CACHE_H
8 
9 /*
10  * As of today we may handle any L1 cache line length right in software.
11  * For that essentially cache line length is a variable not constant.
12  * And to satisfy users of ARCH_DMA_MINALIGN we just use largest line length
13  * that may exist in either L1 or L2 (AKA SLC) caches on ARC.
14  */
15 #define ARCH_DMA_MINALIGN	128
16 
17 #ifndef __ASSEMBLY__
18 
19 void cache_init(void);
20 void flush_n_invalidate_dcache_all(void);
21 void sync_n_cleanup_cache_all(void);
22 
is_ioc_enabled(void)23 static const inline int is_ioc_enabled(void)
24 {
25 	return IS_ENABLED(CONFIG_ARC_DBG_IOC_ENABLE);
26 }
27 
28 /*
29  * We export SLC control functions to use them in platform configuration code.
30  * They maust not be used in any generic code!
31  */
32 void slc_enable(void);
33 void slc_disable(void);
34 
35 #endif /* __ASSEMBLY__ */
36 
37 #endif /* __ASM_ARC_CACHE_H */
38