1/* 2 * Device Tree file for Marvell Armada 375 evaluation board 3 * (DB-88F6720) 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9 * 10 * This file is dual-licensed: you can use it either under the terms 11 * of the GPL or the X11 license, at your option. Note that this dual 12 * licensing only applies to this file, and not this project as a 13 * whole. 14 * 15 * a) This file is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of the 18 * License, or (at your option) any later version. 19 * 20 * This file is distributed in the hope that it will be useful 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * Or, alternatively 26 * 27 * b) Permission is hereby granted, free of charge, to any person 28 * obtaining a copy of this software and associated documentation 29 * files (the "Software"), to deal in the Software without 30 * restriction, including without limitation the rights to use 31 * copy, modify, merge, publish, distribute, sublicense, and/or 32 * sell copies of the Software, and to permit persons to whom the 33 * Software is furnished to do so, subject to the following 34 * conditions: 35 * 36 * The above copyright notice and this permission notice shall be 37 * included in all copies or substantial portions of the Software. 38 * 39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 46 * OTHER DEALINGS IN THE SOFTWARE. 47 */ 48 49/dts-v1/; 50#include <dt-bindings/gpio/gpio.h> 51#include "armada-375.dtsi" 52 53/ { 54 model = "Marvell Armada 375 Development Board"; 55 compatible = "marvell,a375-db", "marvell,armada375"; 56 57 chosen { 58 stdout-path = "serial0:115200n8"; 59 }; 60 61 aliases { 62 /* So that mvebu u-boot can update the MAC addresses */ 63 ethernet0 = ð0; 64 ethernet1 = ð1; 65 spi0 = &spi0; 66 }; 67 68 memory { 69 device_type = "memory"; 70 reg = <0x00000000 0x40000000>; /* 1 GB */ 71 }; 72 73 soc { 74 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 75 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 76 MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000 77 MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>; 78 79 internal-regs { 80 spi@10600 { 81 pinctrl-0 = <&spi0_pins>; 82 pinctrl-names = "default"; 83 /* 84 * SPI conflicts with NAND, so we disable it 85 * here, and select NAND as the enabled device 86 * by default. 87 */ 88 status = "okay"; 89 90 spi-flash@0 { 91 #address-cells = <1>; 92 #size-cells = <1>; 93 compatible = "n25q128a13", "jedec,spi-nor"; 94 reg = <0>; /* Chip select 0 */ 95 spi-max-frequency = <108000000>; 96 }; 97 }; 98 99 i2c@11000 { 100 status = "okay"; 101 clock-frequency = <100000>; 102 pinctrl-0 = <&i2c0_pins>; 103 pinctrl-names = "default"; 104 }; 105 106 i2c@11100 { 107 status = "okay"; 108 clock-frequency = <100000>; 109 pinctrl-0 = <&i2c1_pins>; 110 pinctrl-names = "default"; 111 }; 112 113 serial@12000 { 114 status = "okay"; 115 }; 116 117 pinctrl { 118 sdio_st_pins: sdio-st-pins { 119 marvell,pins = "mpp44", "mpp45"; 120 marvell,function = "gpio"; 121 }; 122 }; 123 124 sata@a0000 { 125 status = "okay"; 126 nr-ports = <2>; 127 }; 128 129 nand: nand@d0000 { 130 pinctrl-0 = <&nand_pins>; 131 pinctrl-names = "default"; 132 status = "okay"; 133 num-cs = <1>; 134 marvell,nand-keep-config; 135 marvell,nand-enable-arbiter; 136 nand-on-flash-bbt; 137 nand-ecc-strength = <4>; 138 nand-ecc-step-size = <512>; 139 140 partition@0 { 141 label = "U-Boot"; 142 reg = <0 0x800000>; 143 }; 144 partition@800000 { 145 label = "Linux"; 146 reg = <0x800000 0x800000>; 147 }; 148 partition@1000000 { 149 label = "Filesystem"; 150 reg = <0x1000000 0x3f000000>; 151 }; 152 }; 153 154 usb@54000 { 155 status = "okay"; 156 }; 157 158 usb3@58000 { 159 status = "okay"; 160 }; 161 162 mvsdio@d4000 { 163 pinctrl-0 = <&sdio_pins &sdio_st_pins>; 164 pinctrl-names = "default"; 165 status = "okay"; 166 cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; 167 wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 168 }; 169 170 mdio { 171 phy0: ethernet-phy@0 { 172 reg = <0>; 173 }; 174 175 phy3: ethernet-phy@3 { 176 reg = <3>; 177 }; 178 }; 179 180 ethernet@f0000 { 181 status = "okay"; 182 183 eth0@c4000 { 184 status = "okay"; 185 phy = <&phy0>; 186 phy-mode = "rgmii-id"; 187 }; 188 189 eth1@c5000 { 190 status = "okay"; 191 phy = <&phy3>; 192 phy-mode = "gmii"; 193 }; 194 }; 195 }; 196 197 pcie-controller { 198 status = "okay"; 199 /* 200 * The two PCIe units are accessible through 201 * standard PCIe slots on the board. 202 */ 203 pcie@1,0 { 204 /* Port 0, Lane 0 */ 205 status = "okay"; 206 }; 207 pcie@2,0 { 208 /* Port 1, Lane 0 */ 209 status = "okay"; 210 }; 211 }; 212 }; 213}; 214