1/* 2 * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC 3 * 4 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> 5 * 6 * Licensed under GPLv2 or later. 7 */ 8 9#include "skeleton.dtsi" 10#include <dt-bindings/pinctrl/at91.h> 11#include <dt-bindings/clock/at91.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/pwm/pwm.h> 15 16/ { 17 model = "Atmel AT91SAM9RL family SoC"; 18 compatible = "atmel,at91sam9rl", "atmel,at91sam9"; 19 interrupt-parent = <&aic>; 20 21 aliases { 22 serial0 = &dbgu; 23 serial1 = &usart0; 24 serial2 = &usart1; 25 serial3 = &usart2; 26 serial4 = &usart3; 27 gpio0 = &pioA; 28 gpio1 = &pioB; 29 gpio2 = &pioC; 30 gpio3 = &pioD; 31 tcb0 = &tcb0; 32 i2c0 = &i2c0; 33 i2c1 = &i2c1; 34 ssc0 = &ssc0; 35 ssc1 = &ssc1; 36 pwm0 = &pwm0; 37 spi0 = &spi0; 38 }; 39 40 cpus { 41 cpu { 42 compatible = "arm,arm926ej-s"; 43 device_type = "cpu"; 44 }; 45 }; 46 47 memory { 48 reg = <0x20000000 0x04000000>; 49 }; 50 51 clocks { 52 slow_xtal: slow_xtal { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <0>; 56 }; 57 58 main_xtal: main_xtal { 59 compatible = "fixed-clock"; 60 #clock-cells = <0>; 61 clock-frequency = <0>; 62 }; 63 64 adc_op_clk: adc_op_clk{ 65 compatible = "fixed-clock"; 66 #clock-cells = <0>; 67 clock-frequency = <1000000>; 68 }; 69 }; 70 71 sram: sram@00300000 { 72 compatible = "mmio-sram"; 73 reg = <0x00300000 0x10000>; 74 }; 75 76 ahb { 77 compatible = "simple-bus"; 78 #address-cells = <1>; 79 #size-cells = <1>; 80 ranges; 81 bootph-all; 82 83 fb0: fb@00500000 { 84 compatible = "atmel,at91sam9rl-lcdc"; 85 reg = <0x00500000 0x1000>; 86 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; 87 pinctrl-names = "default"; 88 pinctrl-0 = <&pinctrl_fb>; 89 clocks = <&lcd_clk>, <&lcd_clk>; 90 clock-names = "hclk", "lcdc_clk"; 91 status = "disabled"; 92 }; 93 94 nand0: nand@40000000 { 95 compatible = "atmel,at91rm9200-nand"; 96 #address-cells = <1>; 97 #size-cells = <1>; 98 reg = <0x40000000 0x10000000>, 99 <0xffffe800 0x200>; 100 atmel,nand-addr-offset = <21>; 101 atmel,nand-cmd-offset = <22>; 102 atmel,nand-has-dma; 103 pinctrl-names = "default"; 104 pinctrl-0 = <&pinctrl_nand>; 105 gpios = <&pioD 17 GPIO_ACTIVE_HIGH>, 106 <&pioB 6 GPIO_ACTIVE_HIGH>, 107 <0>; 108 status = "disabled"; 109 }; 110 111 apb { 112 compatible = "simple-bus"; 113 #address-cells = <1>; 114 #size-cells = <1>; 115 ranges; 116 bootph-all; 117 118 tcb0: timer@fffa0000 { 119 compatible = "atmel,at91rm9200-tcb"; 120 reg = <0xfffa0000 0x100>; 121 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>, 122 <17 IRQ_TYPE_LEVEL_HIGH 0>, 123 <18 IRQ_TYPE_LEVEL_HIGH 0>; 124 clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>; 125 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 126 }; 127 128 mmc0: mmc@fffa4000 { 129 compatible = "atmel,hsmci"; 130 reg = <0xfffa4000 0x600>; 131 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; 132 #address-cells = <1>; 133 #size-cells = <0>; 134 pinctrl-names = "default"; 135 clocks = <&mci0_clk>; 136 clock-names = "mci_clk"; 137 status = "disabled"; 138 }; 139 140 i2c0: i2c@fffa8000 { 141 compatible = "atmel,at91sam9260-i2c"; 142 reg = <0xfffa8000 0x100>; 143 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; 144 #address-cells = <1>; 145 #size-cells = <0>; 146 clocks = <&twi0_clk>; 147 status = "disabled"; 148 }; 149 150 i2c1: i2c@fffac000 { 151 compatible = "atmel,at91sam9260-i2c"; 152 reg = <0xfffac000 0x100>; 153 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 status = "disabled"; 157 }; 158 159 usart0: serial@fffb0000 { 160 compatible = "atmel,at91sam9260-usart"; 161 reg = <0xfffb0000 0x200>; 162 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; 163 atmel,use-dma-rx; 164 atmel,use-dma-tx; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_usart0>; 167 clocks = <&usart0_clk>; 168 clock-names = "usart"; 169 status = "disabled"; 170 }; 171 172 usart1: serial@fffb4000 { 173 compatible = "atmel,at91sam9260-usart"; 174 reg = <0xfffb4000 0x200>; 175 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 176 atmel,use-dma-rx; 177 atmel,use-dma-tx; 178 pinctrl-names = "default"; 179 pinctrl-0 = <&pinctrl_usart1>; 180 clocks = <&usart1_clk>; 181 clock-names = "usart"; 182 status = "disabled"; 183 }; 184 185 usart2: serial@fffb8000 { 186 compatible = "atmel,at91sam9260-usart"; 187 reg = <0xfffb8000 0x200>; 188 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; 189 atmel,use-dma-rx; 190 atmel,use-dma-tx; 191 pinctrl-names = "default"; 192 pinctrl-0 = <&pinctrl_usart2>; 193 clocks = <&usart2_clk>; 194 clock-names = "usart"; 195 status = "disabled"; 196 }; 197 198 usart3: serial@fffbc000 { 199 compatible = "atmel,at91sam9260-usart"; 200 reg = <0xfffbc000 0x200>; 201 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; 202 atmel,use-dma-rx; 203 atmel,use-dma-tx; 204 pinctrl-names = "default"; 205 pinctrl-0 = <&pinctrl_usart3>; 206 clocks = <&usart3_clk>; 207 clock-names = "usart"; 208 status = "disabled"; 209 }; 210 211 ssc0: ssc@fffc0000 { 212 compatible = "atmel,at91sam9rl-ssc"; 213 reg = <0xfffc0000 0x4000>; 214 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 215 pinctrl-names = "default"; 216 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 217 status = "disabled"; 218 }; 219 220 ssc1: ssc@fffc4000 { 221 compatible = "atmel,at91sam9rl-ssc"; 222 reg = <0xfffc4000 0x4000>; 223 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; 224 pinctrl-names = "default"; 225 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 226 status = "disabled"; 227 }; 228 229 pwm0: pwm@fffc8000 { 230 compatible = "atmel,at91sam9rl-pwm"; 231 reg = <0xfffc8000 0x300>; 232 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; 233 #pwm-cells = <3>; 234 clocks = <&pwm_clk>; 235 clock-names = "pwm_clk"; 236 status = "disabled"; 237 }; 238 239 spi0: spi@fffcc000 { 240 #address-cells = <1>; 241 #size-cells = <0>; 242 compatible = "atmel,at91rm9200-spi"; 243 reg = <0xfffcc000 0x200>; 244 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_spi0>; 247 clocks = <&spi0_clk>; 248 clock-names = "spi_clk"; 249 status = "disabled"; 250 }; 251 252 adc0: adc@fffd0000 { 253 compatible = "atmel,at91sam9rl-adc"; 254 reg = <0xfffd0000 0x100>; 255 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; 256 clocks = <&adc_clk>, <&adc_op_clk>; 257 clock-names = "adc_clk", "adc_op_clk"; 258 atmel,adc-use-external-triggers; 259 atmel,adc-channels-used = <0x3f>; 260 atmel,adc-vref = <3300>; 261 atmel,adc-startup-time = <40>; 262 atmel,adc-res = <8 10>; 263 atmel,adc-res-names = "lowres", "highres"; 264 atmel,adc-use-res = "highres"; 265 266 trigger0 { 267 trigger-name = "timer-counter-0"; 268 trigger-value = <0x1>; 269 }; 270 trigger1 { 271 trigger-name = "timer-counter-1"; 272 trigger-value = <0x3>; 273 }; 274 275 trigger2 { 276 trigger-name = "timer-counter-2"; 277 trigger-value = <0x5>; 278 }; 279 280 trigger3 { 281 trigger-name = "external"; 282 trigger-value = <0x13>; 283 trigger-external; 284 }; 285 }; 286 287 usb0: gadget@fffd4000 { 288 #address-cells = <1>; 289 #size-cells = <0>; 290 compatible = "atmel,at91sam9rl-udc"; 291 reg = <0x00600000 0x100000>, 292 <0xfffd4000 0x4000>; 293 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 294 clocks = <&udphs_clk>, <&utmi>; 295 clock-names = "pclk", "hclk"; 296 status = "disabled"; 297 298 ep@0 { 299 reg = <0>; 300 atmel,fifo-size = <64>; 301 atmel,nb-banks = <1>; 302 }; 303 304 ep@1 { 305 reg = <1>; 306 atmel,fifo-size = <1024>; 307 atmel,nb-banks = <2>; 308 atmel,can-dma; 309 atmel,can-isoc; 310 }; 311 312 ep@2 { 313 reg = <2>; 314 atmel,fifo-size = <1024>; 315 atmel,nb-banks = <2>; 316 atmel,can-dma; 317 atmel,can-isoc; 318 }; 319 320 ep@3 { 321 reg = <3>; 322 atmel,fifo-size = <1024>; 323 atmel,nb-banks = <3>; 324 atmel,can-dma; 325 }; 326 327 ep@4 { 328 reg = <4>; 329 atmel,fifo-size = <1024>; 330 atmel,nb-banks = <3>; 331 atmel,can-dma; 332 }; 333 334 ep@5 { 335 reg = <5>; 336 atmel,fifo-size = <1024>; 337 atmel,nb-banks = <3>; 338 atmel,can-dma; 339 atmel,can-isoc; 340 }; 341 342 ep@6 { 343 reg = <6>; 344 atmel,fifo-size = <1024>; 345 atmel,nb-banks = <3>; 346 atmel,can-dma; 347 atmel,can-isoc; 348 }; 349 }; 350 351 dma0: dma-controller@ffffe600 { 352 compatible = "atmel,at91sam9rl-dma"; 353 reg = <0xffffe600 0x200>; 354 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; 355 #dma-cells = <2>; 356 clocks = <&dma0_clk>; 357 clock-names = "dma_clk"; 358 }; 359 360 ramc0: ramc@ffffea00 { 361 compatible = "atmel,at91sam9260-sdramc"; 362 reg = <0xffffea00 0x200>; 363 }; 364 365 aic: interrupt-controller@fffff000 { 366 #interrupt-cells = <3>; 367 compatible = "atmel,at91rm9200-aic"; 368 interrupt-controller; 369 reg = <0xfffff000 0x200>; 370 atmel,external-irqs = <31>; 371 }; 372 373 dbgu: serial@fffff200 { 374 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 375 reg = <0xfffff200 0x200>; 376 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 377 pinctrl-names = "default"; 378 pinctrl-0 = <&pinctrl_dbgu>; 379 clocks = <&mck>; 380 clock-names = "usart"; 381 status = "disabled"; 382 }; 383 384 pinctrl@fffff400 { 385 #address-cells = <1>; 386 #size-cells = <1>; 387 compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; 388 ranges = <0xfffff400 0xfffff400 0x800>; 389 390 atmel,mux-mask = 391 /* A B */ 392 <0xffffffff 0xe05c6738>, /* pioA */ 393 <0xffffffff 0x0000c780>, /* pioB */ 394 <0xffffffff 0xe3ffff0e>, /* pioC */ 395 <0x003fffff 0x0001ff3c>; /* pioD */ 396 bootph-all; 397 398 /* shared pinctrl settings */ 399 adc0 { 400 pinctrl_adc0_ts: adc0_ts-0 { 401 atmel,pins = 402 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>, 403 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>, 404 <AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>, 405 <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; 406 }; 407 408 pinctrl_adc0_ad0: adc0_ad0-0 { 409 atmel,pins = <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; 410 }; 411 412 pinctrl_adc0_ad1: adc0_ad1-0 { 413 atmel,pins = <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; 414 }; 415 416 pinctrl_adc0_ad2: adc0_ad2-0 { 417 atmel,pins = <AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; 418 }; 419 420 pinctrl_adc0_ad3: adc0_ad3-0 { 421 atmel,pins = <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; 422 }; 423 424 pinctrl_adc0_ad4: adc0_ad4-0 { 425 atmel,pins = <AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; 426 }; 427 428 pinctrl_adc0_ad5: adc0_ad5-0 { 429 atmel,pins = <AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; 430 }; 431 432 pinctrl_adc0_adtrg: adc0_adtrg-0 { 433 atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; 434 }; 435 }; 436 437 dbgu { 438 bootph-all; 439 pinctrl_dbgu: dbgu-0 { 440 atmel,pins = 441 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, 442 <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; 443 }; 444 }; 445 446 fb { 447 pinctrl_fb: fb-0 { 448 atmel,pins = 449 <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>, 450 <AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE>, 451 <AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE>, 452 <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>, 453 <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>, 454 <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>, 455 <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>, 456 <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>, 457 <AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE>, 458 <AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_NONE>, 459 <AT91_PIOC 15 AT91_PERIPH_B AT91_PINCTRL_NONE>, 460 <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE>, 461 <AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE>, 462 <AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE>, 463 <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE>, 464 <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE>, 465 <AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>, 466 <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>, 467 <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>, 468 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>, 469 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; 470 }; 471 }; 472 473 i2c_gpio0 { 474 pinctrl_i2c_gpio0: i2c_gpio0-0 { 475 atmel,pins = 476 <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>, 477 <AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; 478 }; 479 }; 480 481 i2c_gpio1 { 482 pinctrl_i2c_gpio1: i2c_gpio1-0 { 483 atmel,pins = 484 <AT91_PIOD 10 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>, 485 <AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; 486 }; 487 }; 488 489 mmc0 { 490 pinctrl_mmc0_clk: mmc0_clk-0 { 491 atmel,pins = 492 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; 493 }; 494 495 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { 496 atmel,pins = 497 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, 498 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 499 }; 500 501 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { 502 atmel,pins = 503 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, 504 <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, 505 <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 506 }; 507 }; 508 509 nand { 510 pinctrl_nand: nand-0 { 511 atmel,pins = 512 <AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>, 513 <AT91_PIOB 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; 514 }; 515 516 pinctrl_nand0_ale_cle: nand_ale_cle-0 { 517 atmel,pins = 518 <AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>, 519 <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; 520 }; 521 522 pinctrl_nand0_oe_we: nand_oe_we-0 { 523 atmel,pins = 524 <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE>, 525 <AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; 526 }; 527 528 pinctrl_nand0_cs: nand_cs-0 { 529 atmel,pins = 530 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; 531 }; 532 }; 533 534 pwm0 { 535 pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 { 536 atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; 537 }; 538 539 pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 { 540 atmel,pins = <AT91_PIOC 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; 541 }; 542 543 pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 { 544 atmel,pins = <AT91_PIOD 14 AT91_PERIPH_B AT91_PINCTRL_NONE>; 545 }; 546 547 pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 { 548 atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; 549 }; 550 551 pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 { 552 atmel,pins = <AT91_PIOC 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; 553 }; 554 555 pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 { 556 atmel,pins = <AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; 557 }; 558 559 pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 { 560 atmel,pins = <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; 561 }; 562 563 pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 { 564 atmel,pins = <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; 565 }; 566 567 pinctrl_pwm0_pwm2_2: pwm0_pwm2-2 { 568 atmel,pins = <AT91_PIOD 16 AT91_PERIPH_B AT91_PINCTRL_NONE>; 569 }; 570 571 pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 { 572 atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; 573 }; 574 575 pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 { 576 atmel,pins = <AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; 577 }; 578 }; 579 580 spi0 { 581 pinctrl_spi0: spi0-0 { 582 atmel,pins = 583 <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>, 584 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>, 585 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; 586 }; 587 }; 588 589 ssc0 { 590 pinctrl_ssc0_tx: ssc0_tx-0 { 591 atmel,pins = 592 <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>, 593 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE>, 594 <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; 595 }; 596 597 pinctrl_ssc0_rx: ssc0_rx-0 { 598 atmel,pins = 599 <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>, 600 <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>, 601 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; 602 }; 603 }; 604 605 ssc1 { 606 pinctrl_ssc1_tx: ssc1_tx-0 { 607 atmel,pins = 608 <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>, 609 <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>, 610 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; 611 }; 612 613 pinctrl_ssc1_rx: ssc1_rx-0 { 614 atmel,pins = 615 <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE>, 616 <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE>, 617 <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>; 618 }; 619 }; 620 621 tcb0 { 622 pinctrl_tcb0_tclk0: tcb0_tclk0-0 { 623 atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; 624 }; 625 626 pinctrl_tcb0_tclk1: tcb0_tclk1-0 { 627 atmel,pins = <AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; 628 }; 629 630 pinctrl_tcb0_tclk2: tcb0_tclk2-0 { 631 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; 632 }; 633 634 pinctrl_tcb0_tioa0: tcb0_tioa0-0 { 635 atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; 636 }; 637 638 pinctrl_tcb0_tioa1: tcb0_tioa1-0 { 639 atmel,pins = <AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; 640 }; 641 642 pinctrl_tcb0_tioa2: tcb0_tioa2-0 { 643 atmel,pins = <AT91_PIOD 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; 644 }; 645 646 pinctrl_tcb0_tiob0: tcb0_tiob0-0 { 647 atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; 648 }; 649 650 pinctrl_tcb0_tiob1: tcb0_tiob1-0 { 651 atmel,pins = <AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; 652 }; 653 654 pinctrl_tcb0_tiob2: tcb0_tiob2-0 { 655 atmel,pins = <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; 656 }; 657 }; 658 659 usart0 { 660 pinctrl_usart0: usart0-0 { 661 atmel,pins = 662 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>, 663 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 664 }; 665 666 pinctrl_usart0_rts: usart0_rts-0 { 667 atmel,pins = 668 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; 669 }; 670 671 pinctrl_usart0_cts: usart0_cts-0 { 672 atmel,pins = 673 <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; 674 }; 675 676 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { 677 atmel,pins = 678 <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>, 679 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; 680 }; 681 682 pinctrl_usart0_dcd: usart0_dcd-0 { 683 atmel,pins = 684 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; 685 }; 686 687 pinctrl_usart0_ri: usart0_ri-0 { 688 atmel,pins = 689 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; 690 }; 691 692 pinctrl_usart0_sck: usart0_sck-0 { 693 atmel,pins = 694 <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; 695 }; 696 }; 697 698 usart1 { 699 pinctrl_usart1: usart1-0 { 700 atmel,pins = 701 <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, 702 <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; 703 }; 704 705 pinctrl_usart1_rts: usart1_rts-0 { 706 atmel,pins = 707 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; 708 }; 709 710 pinctrl_usart1_cts: usart1_cts-0 { 711 atmel,pins = 712 <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; 713 }; 714 715 pinctrl_usart1_sck: usart1_sck-0 { 716 atmel,pins = 717 <AT91_PIOD 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; 718 }; 719 }; 720 721 usart2 { 722 pinctrl_usart2: usart2-0 { 723 atmel,pins = 724 <AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, 725 <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; 726 }; 727 728 pinctrl_usart2_rts: usart2_rts-0 { 729 atmel,pins = 730 <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; 731 }; 732 733 pinctrl_usart2_cts: usart2_cts-0 { 734 atmel,pins = 735 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; 736 }; 737 738 pinctrl_usart2_sck: usart2_sck-0 { 739 atmel,pins = 740 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; 741 }; 742 }; 743 744 usart3 { 745 pinctrl_usart3: usart3-0 { 746 atmel,pins = 747 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, 748 <AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; 749 }; 750 751 pinctrl_usart3_rts: usart3_rts-0 { 752 atmel,pins = 753 <AT91_PIOD 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; 754 }; 755 756 pinctrl_usart3_cts: usart3_cts-0 { 757 atmel,pins = 758 <AT91_PIOD 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; 759 }; 760 761 pinctrl_usart3_sck: usart3_sck-0 { 762 atmel,pins = 763 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; 764 }; 765 }; 766 767 pioA: gpio@fffff400 { 768 compatible = "atmel,at91rm9200-gpio"; 769 reg = <0xfffff400 0x200>; 770 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 771 #gpio-cells = <2>; 772 gpio-controller; 773 interrupt-controller; 774 #interrupt-cells = <2>; 775 clocks = <&pioA_clk>; 776 bootph-all; 777 }; 778 779 pioB: gpio@fffff600 { 780 compatible = "atmel,at91rm9200-gpio"; 781 reg = <0xfffff600 0x200>; 782 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 783 #gpio-cells = <2>; 784 gpio-controller; 785 interrupt-controller; 786 #interrupt-cells = <2>; 787 clocks = <&pioB_clk>; 788 bootph-all; 789 }; 790 791 pioC: gpio@fffff800 { 792 compatible = "atmel,at91rm9200-gpio"; 793 reg = <0xfffff800 0x200>; 794 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 795 #gpio-cells = <2>; 796 gpio-controller; 797 interrupt-controller; 798 #interrupt-cells = <2>; 799 clocks = <&pioC_clk>; 800 bootph-all; 801 }; 802 803 pioD: gpio@fffffa00 { 804 compatible = "atmel,at91rm9200-gpio"; 805 reg = <0xfffffa00 0x200>; 806 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; 807 #gpio-cells = <2>; 808 gpio-controller; 809 interrupt-controller; 810 #interrupt-cells = <2>; 811 clocks = <&pioD_clk>; 812 bootph-all; 813 }; 814 }; 815 816 pmc: pmc@fffffc00 { 817 compatible = "atmel,at91sam9g45-pmc", "syscon"; 818 reg = <0xfffffc00 0x100>; 819 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 820 interrupt-controller; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 #interrupt-cells = <1>; 824 bootph-all; 825 826 main: mainck { 827 compatible = "atmel,at91rm9200-clk-main"; 828 #clock-cells = <0>; 829 interrupts-extended = <&pmc AT91_PMC_MOSCS>; 830 clocks = <&main_xtal>; 831 }; 832 833 plla: pllack@0 { 834 compatible = "atmel,at91rm9200-clk-pll"; 835 #clock-cells = <0>; 836 interrupts-extended = <&pmc AT91_PMC_LOCKA>; 837 clocks = <&main>; 838 reg = <0>; 839 atmel,clk-input-range = <1000000 32000000>; 840 #atmel,pll-clk-output-range-cells = <3>; 841 atmel,pll-clk-output-ranges = <80000000 200000000 0>, 842 <190000000 240000000 2>; 843 }; 844 845 utmi: utmick { 846 compatible = "atmel,at91sam9x5-clk-utmi"; 847 #clock-cells = <0>; 848 interrupt-parent = <&pmc>; 849 interrupts = <AT91_PMC_LOCKU>; 850 clocks = <&main>; 851 }; 852 853 mck: masterck { 854 compatible = "atmel,at91rm9200-clk-master"; 855 #clock-cells = <0>; 856 interrupts-extended = <&pmc AT91_PMC_MCKRDY>; 857 clocks = <&clk32k>, <&main>, <&plla>, <&utmi>; 858 atmel,clk-output-range = <0 94000000>; 859 atmel,clk-divisors = <1 2 4 0>; 860 bootph-all; 861 }; 862 863 prog: progck { 864 compatible = "atmel,at91rm9200-clk-programmable"; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 interrupt-parent = <&pmc>; 868 clocks = <&clk32k>, <&main>, <&plla>, <&utmi>, <&mck>; 869 870 prog0: prog@0 { 871 #clock-cells = <0>; 872 reg = <0>; 873 interrupts = <AT91_PMC_PCKRDY(0)>; 874 }; 875 876 prog1: prog@1 { 877 #clock-cells = <0>; 878 reg = <1>; 879 interrupts = <AT91_PMC_PCKRDY(1)>; 880 }; 881 }; 882 883 systemck { 884 compatible = "atmel,at91rm9200-clk-system"; 885 #address-cells = <1>; 886 #size-cells = <0>; 887 888 pck0: pck0@8 { 889 #clock-cells = <0>; 890 reg = <8>; 891 clocks = <&prog0>; 892 }; 893 894 pck1: pck1@9 { 895 #clock-cells = <0>; 896 reg = <9>; 897 clocks = <&prog1>; 898 }; 899 900 }; 901 902 periphck { 903 compatible = "atmel,at91rm9200-clk-peripheral"; 904 #address-cells = <1>; 905 #size-cells = <0>; 906 clocks = <&mck>; 907 bootph-all; 908 909 pioA_clk: pioA_clk@2 { 910 #clock-cells = <0>; 911 reg = <2>; 912 bootph-all; 913 }; 914 915 pioB_clk: pioB_clk@3 { 916 #clock-cells = <0>; 917 reg = <3>; 918 bootph-all; 919 }; 920 921 pioC_clk: pioC_clk@4 { 922 #clock-cells = <0>; 923 reg = <4>; 924 bootph-all; 925 }; 926 927 pioD_clk: pioD_clk@5 { 928 #clock-cells = <0>; 929 reg = <5>; 930 bootph-all; 931 }; 932 933 usart0_clk: usart0_clk@6 { 934 #clock-cells = <0>; 935 reg = <6>; 936 }; 937 938 usart1_clk: usart1_clk@7 { 939 #clock-cells = <0>; 940 reg = <7>; 941 }; 942 943 usart2_clk: usart2_clk@8 { 944 #clock-cells = <0>; 945 reg = <8>; 946 }; 947 948 usart3_clk: usart3_clk@9 { 949 #clock-cells = <0>; 950 reg = <9>; 951 }; 952 953 mci0_clk: mci0_clk@10 { 954 #clock-cells = <0>; 955 reg = <10>; 956 }; 957 958 twi0_clk: twi0_clk@11 { 959 #clock-cells = <0>; 960 reg = <11>; 961 }; 962 963 twi1_clk: twi1_clk@12 { 964 #clock-cells = <0>; 965 reg = <12>; 966 }; 967 968 spi0_clk: spi0_clk@13 { 969 #clock-cells = <0>; 970 reg = <13>; 971 }; 972 973 ssc0_clk: ssc0_clk@14 { 974 #clock-cells = <0>; 975 reg = <14>; 976 }; 977 978 ssc1_clk: ssc1_clk@15 { 979 #clock-cells = <0>; 980 reg = <15>; 981 }; 982 983 tc0_clk: tc0_clk@16 { 984 #clock-cells = <0>; 985 reg = <16>; 986 }; 987 988 tc1_clk: tc1_clk@17 { 989 #clock-cells = <0>; 990 reg = <17>; 991 }; 992 993 tc2_clk: tc2_clk@18 { 994 #clock-cells = <0>; 995 reg = <18>; 996 }; 997 998 pwm_clk: pwm_clk@19 { 999 #clock-cells = <0>; 1000 reg = <19>; 1001 }; 1002 1003 adc_clk: adc_clk@20 { 1004 #clock-cells = <0>; 1005 reg = <20>; 1006 }; 1007 1008 dma0_clk: dma0_clk@21 { 1009 #clock-cells = <0>; 1010 reg = <21>; 1011 }; 1012 1013 udphs_clk: udphs_clk@22 { 1014 #clock-cells = <0>; 1015 reg = <22>; 1016 }; 1017 1018 lcd_clk: lcd_clk@23 { 1019 #clock-cells = <0>; 1020 reg = <23>; 1021 }; 1022 }; 1023 }; 1024 1025 rstc@fffffd00 { 1026 compatible = "atmel,at91sam9260-rstc"; 1027 reg = <0xfffffd00 0x10>; 1028 clocks = <&clk32k>; 1029 }; 1030 1031 shdwc@fffffd10 { 1032 compatible = "atmel,at91sam9260-shdwc"; 1033 reg = <0xfffffd10 0x10>; 1034 clocks = <&clk32k>; 1035 }; 1036 1037 pit: timer@fffffd30 { 1038 compatible = "atmel,at91sam9260-pit"; 1039 reg = <0xfffffd30 0xf>; 1040 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1041 clocks = <&mck>; 1042 }; 1043 1044 watchdog@fffffd40 { 1045 compatible = "atmel,at91sam9260-wdt"; 1046 reg = <0xfffffd40 0x10>; 1047 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1048 clocks = <&clk32k>; 1049 status = "disabled"; 1050 }; 1051 1052 sckc@fffffd50 { 1053 compatible = "atmel,at91sam9x5-sckc"; 1054 reg = <0xfffffd50 0x4>; 1055 1056 slow_osc: slow_osc { 1057 compatible = "atmel,at91sam9x5-clk-slow-osc"; 1058 #clock-cells = <0>; 1059 atmel,startup-time-usec = <1200000>; 1060 clocks = <&slow_xtal>; 1061 }; 1062 1063 slow_rc_osc: slow_rc_osc { 1064 compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; 1065 #clock-cells = <0>; 1066 atmel,startup-time-usec = <75>; 1067 clock-frequency = <32768>; 1068 clock-accuracy = <50000000>; 1069 }; 1070 1071 clk32k: slck { 1072 compatible = "atmel,at91sam9x5-clk-slow"; 1073 #clock-cells = <0>; 1074 clocks = <&slow_rc_osc &slow_osc>; 1075 }; 1076 }; 1077 1078 rtc@fffffd20 { 1079 compatible = "atmel,at91sam9260-rtt"; 1080 reg = <0xfffffd20 0x10>; 1081 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1082 clocks = <&clk32k>; 1083 status = "disabled"; 1084 }; 1085 1086 gpbr: syscon@fffffd60 { 1087 compatible = "atmel,at91sam9260-gpbr", "syscon"; 1088 reg = <0xfffffd60 0x10>; 1089 status = "disabled"; 1090 }; 1091 1092 rtc@fffffe00 { 1093 compatible = "atmel,at91rm9200-rtc"; 1094 reg = <0xfffffe00 0x40>; 1095 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1096 clocks = <&clk32k>; 1097 status = "disabled"; 1098 }; 1099 1100 }; 1101 }; 1102 1103 i2c-gpio-0 { 1104 compatible = "i2c-gpio"; 1105 gpios = <&pioA 23 GPIO_ACTIVE_HIGH>, /* sda */ 1106 <&pioA 24 GPIO_ACTIVE_HIGH>; /* scl */ 1107 i2c-gpio,sda-open-drain; 1108 i2c-gpio,scl-open-drain; 1109 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 pinctrl-names = "default"; 1113 pinctrl-0 = <&pinctrl_i2c_gpio0>; 1114 status = "disabled"; 1115 }; 1116 1117 i2c-gpio-1 { 1118 compatible = "i2c-gpio"; 1119 gpios = <&pioD 10 GPIO_ACTIVE_HIGH>, /* sda */ 1120 <&pioD 11 GPIO_ACTIVE_HIGH>; /* scl */ 1121 i2c-gpio,sda-open-drain; 1122 i2c-gpio,scl-open-drain; 1123 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 pinctrl-names = "default"; 1127 pinctrl-0 = <&pinctrl_i2c_gpio1>; 1128 status = "disabled"; 1129 }; 1130}; 1131