1// SPDX-License-Identifier: GPL-2.0+ OR X11 2/* 3 * Copyright 2020-2021 NXP 4 * Copyright 2016 Freescale Semiconductor 5 */ 6 7/include/ "skeleton64.dtsi" 8 9/ { 10 compatible = "fsl,ls1012a"; 11 interrupt-parent = <&gic>; 12 13 sysclk: sysclk { 14 compatible = "fixed-clock"; 15 #clock-cells = <0>; 16 clock-frequency = <100000000>; 17 clock-output-names = "sysclk"; 18 }; 19 20 gic: interrupt-controller@1400000 { 21 compatible = "arm,gic-400"; 22 #interrupt-cells = <3>; 23 interrupt-controller; 24 reg = <0x0 0x1401000 0 0x1000>, /* GICD */ 25 <0x0 0x1402000 0 0x2000>, /* GICC */ 26 <0x0 0x1404000 0 0x2000>, /* GICH */ 27 <0x0 0x1406000 0 0x2000>; /* GICV */ 28 interrupts = <1 9 0xf08>; 29 }; 30 31 soc { 32 compatible = "simple-bus"; 33 #address-cells = <2>; 34 #size-cells = <2>; 35 ranges; 36 37 sfp: efuse@1e80000 { 38 compatible = "fsl,ls1021a-sfp"; 39 reg = <0x0 0x1e80000 0x0 0x1000>; 40 clocks = <&clockgen 4 3>; 41 clock-names = "sfp"; 42 }; 43 44 clockgen: clocking@1ee1000 { 45 compatible = "fsl,ls1012a-clockgen"; 46 reg = <0x0 0x1ee1000 0x0 0x1000>; 47 #clock-cells = <2>; 48 clocks = <&sysclk>; 49 }; 50 51 dspi0: dspi@2100000 { 52 compatible = "fsl,vf610-dspi"; 53 #address-cells = <1>; 54 #size-cells = <0>; 55 reg = <0x0 0x2100000 0x0 0x10000>; 56 interrupts = <0 64 0x4>; 57 clock-names = "dspi"; 58 clocks = <&clockgen 4 0>; 59 spi-num-chipselects = <6>; 60 big-endian; 61 status = "disabled"; 62 }; 63 64 esdhc0: esdhc@1560000 { 65 compatible = "fsl,esdhc"; 66 reg = <0x0 0x1560000 0x0 0x10000>; 67 interrupts = <0 62 0x4>; 68 big-endian; 69 bus-width = <4>; 70 }; 71 72 esdhc1: esdhc@1580000 { 73 compatible = "fsl,esdhc"; 74 reg = <0x0 0x1580000 0x0 0x10000>; 75 interrupts = <0 65 0x4>; 76 big-endian; 77 non-removable; 78 bus-width = <4>; 79 }; 80 81 crypto: crypto@1700000 { 82 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 83 "fsl,sec-v4.0"; 84 fsl,sec-era = <8>; 85 #address-cells = <1>; 86 #size-cells = <1>; 87 ranges = <0x0 0x00 0x1700000 0x100000>; 88 reg = <0x00 0x1700000 0x0 0x100000>; 89 interrupts = <0 75 0x4>; 90 dma-coherent; 91 92 sec_jr0: jr@10000 { 93 compatible = "fsl,sec-v5.4-job-ring", 94 "fsl,sec-v5.0-job-ring", 95 "fsl,sec-v4.0-job-ring"; 96 reg = <0x10000 0x10000>; 97 interrupts = <0 71 0x4>; 98 }; 99 100 sec_jr1: jr@20000 { 101 compatible = "fsl,sec-v5.4-job-ring", 102 "fsl,sec-v5.0-job-ring", 103 "fsl,sec-v4.0-job-ring"; 104 reg = <0x20000 0x10000>; 105 interrupts = <0 72 0x4>; 106 }; 107 108 sec_jr2: jr@30000 { 109 compatible = "fsl,sec-v5.4-job-ring", 110 "fsl,sec-v5.0-job-ring", 111 "fsl,sec-v4.0-job-ring"; 112 reg = <0x30000 0x10000>; 113 interrupts = <0 73 0x4>; 114 }; 115 116 sec_jr3: jr@40000 { 117 compatible = "fsl,sec-v5.4-job-ring", 118 "fsl,sec-v5.0-job-ring", 119 "fsl,sec-v4.0-job-ring"; 120 reg = <0x40000 0x10000>; 121 interrupts = <0 74 0x4>; 122 }; 123 }; 124 125 gpio0: gpio@2300000 { 126 compatible = "fsl,qoriq-gpio"; 127 reg = <0x0 0x2300000 0x0 0x10000>; 128 interrupts = <0 66 0x4>; 129 gpio-controller; 130 #gpio-cells = <2>; 131 interrupt-controller; 132 #interrupt-cells = <2>; 133 }; 134 135 gpio1: gpio@2310000 { 136 compatible = "fsl,qoriq-gpio"; 137 reg = <0x0 0x2310000 0x0 0x10000>; 138 interrupts = <0 67 0x4>; 139 gpio-controller; 140 #gpio-cells = <2>; 141 interrupt-controller; 142 #interrupt-cells = <2>; 143 }; 144 145 i2c0: i2c@2180000 { 146 compatible = "fsl,vf610-i2c"; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 reg = <0x0 0x2180000 0x0 0x10000>; 150 interrupts = <0 56 0x4>; 151 clock-names = "i2c"; 152 clocks = <&clockgen 4 0>; 153 status = "disabled"; 154 }; 155 156 i2c1: i2c@2190000 { 157 compatible = "fsl,vf610-i2c"; 158 #address-cells = <1>; 159 #size-cells = <0>; 160 reg = <0x0 0x2190000 0x0 0x10000>; 161 interrupts = <0 57 0x4>; 162 clock-names = "i2c"; 163 clocks = <&clockgen 4 0>; 164 status = "disabled"; 165 }; 166 167 duart0: serial@21c0500 { 168 compatible = "fsl,ns16550", "ns16550a"; 169 reg = <0x00 0x21c0500 0x0 0x100>; 170 interrupts = <0 54 0x4>; 171 clocks = <&clockgen 4 0>; 172 }; 173 174 duart1: serial@21c0600 { 175 compatible = "fsl,ns16550", "ns16550a"; 176 reg = <0x00 0x21c0600 0x0 0x100>; 177 interrupts = <0 54 0x4>; 178 clocks = <&clockgen 4 0>; 179 }; 180 181 qspi: quadspi@1550000 { 182 compatible = "fsl,ls1021a-qspi"; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 reg = <0x0 0x1550000 0x0 0x10000>, 186 <0x0 0x40000000 0x0 0x4000000>; 187 reg-names = "QuadSPI", "QuadSPI-memory"; 188 status = "disabled"; 189 }; 190 191 pcie1: pcie@3400000 { 192 compatible = "fsl,ls-pcie", "snps,dw-pcie"; 193 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ 194 0x00 0x03480000 0x0 0x40000 /* lut registers */ 195 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ 196 0x40 0x00000000 0x0 0x20000>; /* configuration space */ 197 reg-names = "dbi", "lut", "ctrl", "config"; 198 big-endian; 199 #address-cells = <3>; 200 #size-cells = <2>; 201 device_type = "pci"; 202 bus-range = <0x0 0xff>; 203 ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */ 204 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 205 }; 206 207 sata: sata@3200000 { 208 compatible = "fsl,ls1012a-ahci"; 209 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ 210 0x0 0x20140520 0x0 0x4>; /* ecc sata addr */ 211 reg-names = "ahci", "sata-ecc"; 212 interrupts = <0 69 4>; 213 clocks = <&clockgen 4 0>; 214 status = "disabled"; 215 }; 216 217 usb0: usb2@8600000 { 218 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; 219 reg = <0x0 0x8600000 0x0 0x1000>; 220 interrupts = <0 139 0x4>; 221 dr_mode = "host"; 222 fsl,usb-erratum-a005697; 223 }; 224 225 usb1: usb3@2f00000 { 226 compatible = "fsl,layerscape-dwc3"; 227 reg = <0x0 0x2f00000 0x0 0x10000>; 228 interrupts = <0 61 0x4>; 229 dr_mode = "host"; 230 }; 231 }; 232}; 233