1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) 2020
4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
5 */
6
7#include "armv7-m.dtsi"
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/imxrt1020-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/memory/imxrt-sdram.h>
12
13/ {
14	#address-cells = <1>;
15	#size-cells = <1>;
16
17	aliases {
18		gpio0 = &gpio1;
19		gpio1 = &gpio2;
20		gpio2 = &gpio3;
21		mmc0 = &usdhc1;
22		serial0 = &lpuart1;
23	};
24
25	clocks {
26		ckil {
27			compatible = "fsl,imx-ckil", "fixed-clock";
28			#clock-cells = <0>;
29			clock-frequency = <32768>;
30		};
31
32		ckih1 {
33			compatible = "fsl,imx-ckih1", "fixed-clock";
34			#clock-cells = <0>;
35			clock-frequency = <0>;
36		};
37
38		osc: osc {
39			compatible = "fsl,imx-osc", "fixed-clock";
40			#clock-cells = <0>;
41			clock-frequency = <24000000>;
42		};
43	};
44
45	soc {
46		semc: semc@402f0000 {
47			compatible = "fsl,imxrt-semc";
48			reg = <0x402f0000 0x4000>;
49			clocks = <&clks IMXRT1020_CLK_SEMC>;
50			pinctrl-0 = <&pinctrl_semc>;
51			pinctrl-names = "default";
52			status = "okay";
53		};
54
55		lpuart1: serial@40184000 {
56			compatible = "fsl,imxrt-lpuart";
57			reg = <0x40184000 0x4000>;
58			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
59			clocks = <&clks IMXRT1020_CLK_LPUART1>;
60			clock-names = "per";
61			status = "disabled";
62		};
63
64		iomuxc: iomuxc@401f8000 {
65			compatible = "fsl,imxrt-iomuxc";
66			reg = <0x401f8000 0x4000>;
67		};
68
69		anatop: anatop@400d8000 {
70			compatible = "fsl,imxrt-anatop";
71			reg = <0x400d8000 0x4000>;
72		};
73
74		clks: ccm@400fc000 {
75			compatible = "fsl,imxrt1020-ccm";
76			reg = <0x400fc000 0x4000>;
77			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
78				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
79			#clock-cells = <1>;
80		};
81
82		usdhc1: usdhc@402c0000 {
83			compatible = "fsl,imxrt-usdhc";
84			reg = <0x402c0000 0x10000>;
85			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
86			clocks = <&clks IMXRT1020_CLK_USDHC1>;
87			clock-names = "per";
88			bus-width = <4>;
89			fsl,tuning-start-tap = <20>;
90			fsl,tuning-step= <2>;
91			status = "disabled";
92		};
93
94		gpio1: gpio@401b8000 {
95			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
96			reg = <0x401b8000 0x4000>;
97			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
98				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
99			gpio-controller;
100			#gpio-cells = <2>;
101			interrupt-controller;
102			#interrupt-cells = <2>;
103		};
104
105		gpio2: gpio@401bc000 {
106			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
107			reg = <0x401bc000 0x4000>;
108			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
109				<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
110			gpio-controller;
111			#gpio-cells = <2>;
112			interrupt-controller;
113			#interrupt-cells = <2>;
114		};
115
116		gpio3: gpio@401c0000 {
117			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
118			reg = <0x401c0000 0x4000>;
119			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
120				<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
121			gpio-controller;
122			#gpio-cells = <2>;
123			interrupt-controller;
124			#interrupt-cells = <2>;
125		};
126
127		gpio5: gpio@400c0000 {
128			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
129			reg = <0x400c0000 0x4000>;
130			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
131				<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
132			gpio-controller;
133			#gpio-cells = <2>;
134			interrupt-controller;
135			#interrupt-cells = <2>;
136		};
137
138		gpt1: gpt1@401ec000 {
139			compatible = "fsl,imxrt-gpt";
140			reg = <0x401ec000 0x4000>;
141			interrupts = <100>;
142			clocks = <&osc>;
143			status = "disabled";
144		};
145	};
146};
147