1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2025 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
7#include "mt7987-pinctrl-u-boot.dtsi"
8
9/ {
10	cpus {
11		cpu@0 {
12			mediatek,hwver = <&hwver>;
13		};
14
15		cpu@1 {
16			mediatek,hwver = <&hwver>;
17		};
18
19		cpu@2 {
20			mediatek,hwver = <&hwver>;
21		};
22
23		cpu@3 {
24			mediatek,hwver = <&hwver>;
25		};
26	};
27
28	reserved-memory {
29		/delete-node/ wmcpu-reserved@50000000;
30	};
31};
32
33&i2c0 {
34	pinctrl-names = "default";
35	pinctrl-0 = <&i2c0_pins>;
36	status = "okay";
37};
38
39&pcie0 {
40	pinctrl-names = "default";
41	pinctrl-0 = <&pcie0_pins>;
42	status = "okay";
43};
44
45&pcie1 {
46	pinctrl-names = "default";
47	pinctrl-0 = <&pcie1_pins>;
48	status = "disabled";
49};
50
51&spi0 {
52	compatible = "mediatek,ipm-spi";
53	clocks = <&infracfg CLK_INFRA_104M_SPI0>,
54		 <&topckgen CLK_TOP_SPI_SEL>;
55	clock-names = "spi-clk", "sel-clk";
56};
57
58&spi1 {
59	compatible = "mediatek,ipm-spi";
60	clocks = <&infracfg CLK_INFRA_104M_SPI1>,
61		 <&topckgen CLK_TOP_SPIM_MST_SEL>;
62	clock-names = "spi-clk", "sel-clk";
63};
64
65&spi2 {
66	compatible = "mediatek,ipm-spi";
67	clocks = <&infracfg CLK_INFRA_104M_SPI2_BCK>,
68		 <&topckgen CLK_TOP_SPI_SEL>;
69	clock-names = "spi-clk", "sel-clk";
70};
71