1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4 */
5
6#include "rockchip-u-boot.dtsi"
7
8/ {
9	aliases {
10		mmc0 = &emmc;
11		mmc1 = &sdmmc;
12	};
13
14	chosen {
15		u-boot,spl-boot-order = &emmc, &sdmmc;
16	};
17
18	dmc {
19		bootph-all;
20		compatible = "rockchip,px30-dmc", "syscon";
21		reg = <0x0 0xff2a0000 0x0 0x1000>;
22	};
23
24	rng: rng@ff0b0000 {
25		compatible = "rockchip,cryptov2-rng";
26		reg = <0x0 0xff0b0000 0x0 0x4000>;
27	};
28};
29
30&uart2 {
31	clock-frequency = <24000000>;
32	bootph-all;
33};
34
35&uart2m0_xfer {
36	bootph-all;
37};
38
39&uart5 {
40	clock-frequency = <24000000>;
41	bootph-all;
42};
43
44&uart5_cts {
45	bootph-all;
46};
47
48&uart5_rts {
49	bootph-all;
50};
51
52&uart5_xfer {
53	bootph-all;
54};
55
56&sdmmc {
57	bootph-all;
58
59	/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
60	u-boot,spl-fifo-mode;
61};
62
63&emmc {
64	bootph-all;
65
66	/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
67	u-boot,spl-fifo-mode;
68};
69
70&grf {
71	bootph-all;
72};
73
74&pmugrf {
75	bootph-all;
76};
77
78&xin24m {
79	bootph-all;
80};
81
82&cru {
83	bootph-all;
84	/delete-property/ assigned-clocks;
85	/delete-property/ assigned-clock-rates;
86};
87
88&pmucru {
89	bootph-all;
90	/delete-property/ assigned-clocks;
91	/delete-property/ assigned-clock-rates;
92};
93
94&saradc {
95	bootph-all;
96	status = "okay";
97};
98
99&gpio0 {
100	bootph-all;
101	gpio-ranges = <&pinctrl 0 0 32>;
102};
103
104&gpio1 {
105	bootph-all;
106	gpio-ranges = <&pinctrl 0 32 32>;
107};
108
109&gpio2 {
110	bootph-all;
111	gpio-ranges = <&pinctrl 0 64 32>;
112};
113
114&gpio3 {
115	bootph-all;
116	gpio-ranges = <&pinctrl 0 96 32>;
117};
118