1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC.
4 *
5 * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
6 *
7 * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
8 */
9
10#include "skeleton.dtsi"
11#include <dt-bindings/dma/at91.h>
12#include <dt-bindings/pinctrl/at91.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/clk/at91.h>
16
17/{
18	model = "Microchip SAM9X60 SoC";
19	compatible = "microchip,sam9x60";
20	interrupt-parent = <&aic>;
21
22	aliases {
23		serial0 = &dbgu;
24		gpio0 = &pioA;
25		gpio1 = &pioB;
26		gpio2 = &pioC;
27		gpio3 = &pioD;
28		spi0 = &qspi;
29	};
30
31	cpus {
32		#address-cells = <1>;
33		#size-cells = <0>;
34
35		ARM9260_0: cpu@0 {
36			device_type = "cpu";
37			compatible = "arm,arm926ej-s";
38			clocks = <&pmc PMC_TYPE_CORE 19>, <&pmc PMC_TYPE_CORE 11>, <&main_xtal>;
39			clock-names = "cpu", "master", "xtal";
40		};
41	};
42
43	clocks {
44		slow_rc_osc: slow_rc_osc {
45			compatible = "fixed-clock";
46			#clock-cells = <0>;
47			clock-frequency = <18500>;
48		};
49
50		main_rc: main_rc {
51			compatible = "fixed-clock";
52			#clock-cells = <0>;
53			clock-frequency = <12000000>;
54		};
55
56		slow_xtal: slow_xtal {
57			compatible = "fixed-clock";
58			#clock-cells = <0>;
59		};
60
61		main_xtal: main_xtal {
62			compatible = "fixed-clock";
63			#clock-cells = <0>;
64		};
65	};
66
67	ahb {
68		compatible = "simple-bus";
69		#address-cells = <1>;
70		#size-cells = <1>;
71		ranges;
72
73		usb0: gadget@500000 {
74			#address-cells = <1>;
75			#size-cells = <0>;
76			compatible = "microchip,sam9x60-udc";
77			reg = <0x500000 0x100000>,
78				<0xf803c000 0x400>;
79			clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE 8>;
80			clock-names = "pclk", "hclk";
81			assigned-clocks = <&pmc PMC_TYPE_CORE 8>;
82			assigned-clock-rates = <480000000>;
83			status = "disabled";
84		};
85
86		usb1: usb@600000 {
87			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
88			reg = <0x00600000 0x100000>;
89			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 21>;
90			clock-names = "ohci_clk", "hclk", "uhpck";
91			status = "disabled";
92		};
93
94		usb2: usb@700000 {
95			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
96			reg = <0x00700000 0x100000>;
97			clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_PERIPHERAL 22>;
98			clock-names = "usb_clk", "ehci_clk";
99			assigned-clocks = <&pmc PMC_TYPE_CORE 8>;
100			assigned-clock-rates = <480000000>;
101			status = "disabled";
102		};
103
104		ebi: ebi@10000000 {
105			compatible = "microchip,sam9x60-ebi";
106			#address-cells = <2>;
107			#size-cells = <1>;
108			atmel,smc = <&smc>;
109			microchip,sfr = <&sfr>;
110			reg = <0x10000000 0x60000000>;
111			ranges = <0x0 0x0 0x10000000 0x10000000
112				  0x1 0x0 0x20000000 0x10000000
113				  0x2 0x0 0x30000000 0x10000000
114				  0x3 0x0 0x40000000 0x10000000
115				  0x4 0x0 0x50000000 0x10000000
116				  0x5 0x0 0x60000000 0x10000000>;
117			clocks = <&pmc PMC_TYPE_CORE 11>;
118			status = "disabled";
119
120			nand_controller: nand-controller {
121				compatible = "microchip,sam9x60-nand-controller";
122				ecc-engine = <&pmecc>;
123				#address-cells = <2>;
124				#size-cells = <1>;
125				ranges;
126				status = "disabled";
127			};
128		};
129
130		sdhci0: sdhci-host@80000000 {
131			compatible = "microchip,sam9x60-sdhci";
132			reg = <0x80000000 0x300>;
133			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
134			clock-names = "hclock", "multclk";
135			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
136			assigned-clock-rates = <100000000>;
137			assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */
138			bus-width = <4>;
139		};
140
141		sdhci1: sdhci-host@90000000 {
142			compatible = "microchip,sam9x60-sdhci";
143			reg = <0x90000000 0x300>;
144			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
145			clock-names = "hclock", "multclk";
146			assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
147			assigned-clock-rates = <100000000>;
148			assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */
149			bus-width = <4>;
150		};
151
152		apb {
153			compatible = "simple-bus";
154			#address-cells = <1>;
155			#size-cells = <1>;
156			ranges;
157
158			qspi: spi@f0014000 {
159				compatible = "microchip,sam9x60-qspi";
160				reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
161				reg-names = "qspi_base", "qspi_mmap";
162				clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 18>; /* ID_QSPI */
163				clock-names = "pclk", "qspick";
164				#address-cells = <1>;
165				#size-cells = <0>;
166				status = "disabled";
167			};
168
169			pit64b0: timer@f0028000 {
170				compatible = "microchip,sam9x60-pit64b";
171				reg = <0xf0028000 0xec>;
172				clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
173				clock-names = "pclk", "gclk";
174			};
175
176			flx0: flexcom@f801c600 {
177				compatible = "atmel,sama5d2-flexcom";
178				reg = <0xf801c000 0x200>;
179				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
180				#address-cells = <1>;
181				#size-cells = <1>;
182				ranges = <0x0 0xf801c000 0x800>;
183				status = "disabled";
184			};
185
186			macb0: ethernet@f802c000 {
187				compatible = "cdns,sam9x60-macb", "cdns,macb";
188				reg = <0xf802c000 0x100>;
189				clock-names = "hclk", "pclk";
190				clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
191				status = "disabled";
192			};
193
194			sfr: sfr@f8050000 {
195				compatible = "microchip,sam9x60-sfr", "syscon";
196				reg = <0xf8050000 0x100>;
197			};
198
199			pmecc: ecc-engine@ffffe000 {
200				compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
201				reg = <0xffffe000 0x300>,
202				      <0xffffe600 0x100>;
203			};
204
205			smc: smc@ffffea00 {
206				compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
207				reg = <0xffffea00 0x100>;
208			};
209
210			aic: interrupt-controller@fffff100 {
211				compatible = "microchip,sam9x60-aic";
212				#interrupt-cells = <3>;
213				interrupt-controller;
214				reg = <0xfffff100 0x100>;
215				atmel,external-irqs = <31>;
216			};
217
218			dbgu: serial@fffff200 {
219				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
220				reg = <0xfffff200 0x200>;
221				clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
222				clock-names = "usart";
223			};
224
225			pinctrl: pinctrl@fffff400 {
226				#address-cells = <1>;
227				#size-cells = <1>;
228				compatible = "microchip,sam9x60-pinctrl", "simple-mfd";
229				ranges = <0xfffff400 0xfffff400 0x800>;
230
231				/* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */
232				atmel,mux-mask = <
233						  /*     A       B       C       */
234						  0xffffffff 0xffe03fff 0xef00019d       /* pioA */
235						  0x03ffffff 0x02fc7e7f 0x00780000       /* pioB */
236						  0xffffffff 0xffffffff 0xf83fffff       /* pioC */
237						  0x003fffff 0x003f8000 0x00000000       /* pioD */
238						  >;
239
240				pioA: gpio@fffff400 {
241					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
242					reg = <0xfffff400 0x200>;
243					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
244					#gpio-cells = <2>;
245					gpio-controller;
246					interrupt-controller;
247					#interrupt-cells = <2>;
248					clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
249				};
250
251				pioB: gpio@fffff600 {
252					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
253					reg = <0xfffff600 0x200>;
254					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
255					#gpio-cells = <2>;
256					gpio-controller;
257					#gpio-lines = <26>;
258					interrupt-controller;
259					#interrupt-cells = <2>;
260					clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
261				};
262
263				pioC: gpio@fffff800 {
264					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
265					reg = <0xfffff800 0x200>;
266					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
267					#gpio-cells = <2>;
268					gpio-controller;
269					interrupt-controller;
270					#interrupt-cells = <2>;
271					clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
272				};
273
274				pioD: gpio@fffffa00 {
275					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
276					reg = <0xfffffa00 0x200>;
277					interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
278					#gpio-cells = <2>;
279					gpio-controller;
280					#gpio-lines = <22>;
281					interrupt-controller;
282					#interrupt-cells = <2>;
283					clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
284				};
285			};
286
287			pmc: pmc@fffffc00 {
288				compatible = "microchip,sam9x60-pmc";
289				reg = <0xfffffc00 0x200>;
290				#clock-cells = <2>;
291				clocks = <&clk32 1>, <&clk32 0>, <&main_xtal>, <&main_rc>;
292				clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
293				status = "okay";
294			};
295
296			reset_controller: rstc@fffffe00 {
297				compatible = "microchip,sam9x60-rstc";
298				reg = <0xfffffe00 0x10>;
299				clocks = <&clk32 0>;
300			};
301
302			pit: timer@fffffe40 {
303				compatible = "atmel,at91sam9260-pit";
304				reg = <0xfffffe40 0x10>;
305				clocks = <&pmc PMC_TYPE_CORE 11>; /* ID_MCK. */
306			};
307
308			clk32: sckc@fffffe50 {
309				compatible = "microchip,sam9x60-sckc";
310				reg = <0xfffffe50 0x4>;
311				clocks = <&slow_rc_osc>, <&slow_xtal>;
312				#clock-cells = <1>;
313			};
314
315			watchdog: watchdog@ffffff80 {
316				compatible = "microchip,sam9x60-wdt";
317				reg = <0xffffff80 0x24>;
318				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
319				clocks = <&clk32 0>;
320				status = "disabled";
321			};
322		};
323	};
324
325	onewire_tm: onewire {
326		compatible = "w1-gpio";
327		status = "disabled";
328	};
329};
330