1/* 2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC 3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC 4 * 5 * Copyright (C) 2013 Atmel, 6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> 7 * 8 * Licensed under GPLv2 or later. 9 */ 10 11#include "skeleton.dtsi" 12#include <dt-bindings/dma/at91.h> 13#include <dt-bindings/pinctrl/at91.h> 14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/clock/at91.h> 17 18/ { 19 model = "Atmel SAMA5D3 family SoC"; 20 compatible = "atmel,sama5d3", "atmel,sama5"; 21 interrupt-parent = <&aic>; 22 23 aliases { 24 serial0 = &dbgu; 25 serial1 = &usart0; 26 serial2 = &usart1; 27 serial3 = &usart2; 28 serial4 = &usart3; 29 serial5 = &uart0; 30 gpio0 = &pioA; 31 gpio1 = &pioB; 32 gpio2 = &pioC; 33 gpio3 = &pioD; 34 gpio4 = &pioE; 35 tcb0 = &tcb0; 36 i2c0 = &i2c0; 37 i2c1 = &i2c1; 38 i2c2 = &i2c2; 39 ssc0 = &ssc0; 40 ssc1 = &ssc1; 41 pwm0 = &pwm0; 42 }; 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a5"; 49 reg = <0x0>; 50 }; 51 }; 52 53 pmu { 54 compatible = "arm,cortex-a5-pmu"; 55 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>; 56 }; 57 58 memory { 59 reg = <0x20000000 0x8000000>; 60 }; 61 62 clocks { 63 slow_xtal: slow_xtal { 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <0>; 67 }; 68 69 main_xtal: main_xtal { 70 compatible = "fixed-clock"; 71 #clock-cells = <0>; 72 clock-frequency = <0>; 73 }; 74 75 adc_op_clk: adc_op_clk{ 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <1000000>; 79 }; 80 }; 81 82 sram: sram@00300000 { 83 compatible = "mmio-sram"; 84 reg = <0x00300000 0x20000>; 85 }; 86 87 ahb { 88 compatible = "simple-bus"; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 ranges; 92 bootph-all; 93 94 apb { 95 compatible = "simple-bus"; 96 #address-cells = <1>; 97 #size-cells = <1>; 98 ranges; 99 bootph-all; 100 101 mmc0: mmc@f0000000 { 102 compatible = "atmel,hsmci"; 103 reg = <0xf0000000 0x600>; 104 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; 105 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>; 106 dma-names = "rxtx"; 107 pinctrl-names = "default"; 108 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; 109 status = "disabled"; 110 #address-cells = <1>; 111 #size-cells = <0>; 112 clocks = <&mci0_clk>; 113 clock-names = "mci_clk"; 114 }; 115 116 spi0: spi@f0004000 { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 compatible = "atmel,at91rm9200-spi"; 120 reg = <0xf0004000 0x100>; 121 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; 122 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>, 123 <&dma0 2 AT91_DMA_CFG_PER_ID(2)>; 124 dma-names = "tx", "rx"; 125 pinctrl-names = "default"; 126 pinctrl-0 = <&pinctrl_spi0>; 127 clocks = <&spi0_clk>; 128 clock-names = "spi_clk"; 129 status = "disabled"; 130 }; 131 132 ssc0: ssc@f0008000 { 133 compatible = "atmel,at91sam9g45-ssc"; 134 reg = <0xf0008000 0x4000>; 135 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; 136 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>, 137 <&dma0 2 AT91_DMA_CFG_PER_ID(14)>; 138 dma-names = "tx", "rx"; 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 141 clocks = <&ssc0_clk>; 142 clock-names = "pclk"; 143 status = "disabled"; 144 }; 145 146 tcb0: timer@f0010000 { 147 compatible = "atmel,at91sam9x5-tcb"; 148 reg = <0xf0010000 0x100>; 149 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; 150 clocks = <&tcb0_clk>, <&clk32k>; 151 clock-names = "t0_clk", "slow_clk"; 152 }; 153 154 i2c0: i2c@f0014000 { 155 compatible = "atmel,at91sam9x5-i2c"; 156 reg = <0xf0014000 0x4000>; 157 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>; 158 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>, 159 <&dma0 2 AT91_DMA_CFG_PER_ID(8)>; 160 dma-names = "tx", "rx"; 161 pinctrl-names = "default"; 162 pinctrl-0 = <&pinctrl_i2c0>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 clocks = <&twi0_clk>; 166 status = "disabled"; 167 }; 168 169 i2c1: i2c@f0018000 { 170 compatible = "atmel,at91sam9x5-i2c"; 171 reg = <0xf0018000 0x4000>; 172 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>; 173 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>, 174 <&dma0 2 AT91_DMA_CFG_PER_ID(10)>; 175 dma-names = "tx", "rx"; 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pinctrl_i2c1>; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 clocks = <&twi1_clk>; 181 status = "disabled"; 182 }; 183 184 usart0: serial@f001c000 { 185 compatible = "atmel,at91sam9260-usart"; 186 reg = <0xf001c000 0x100>; 187 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; 188 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, 189 <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 190 dma-names = "tx", "rx"; 191 pinctrl-names = "default"; 192 pinctrl-0 = <&pinctrl_usart0>; 193 clocks = <&usart0_clk>; 194 clock-names = "usart"; 195 status = "disabled"; 196 }; 197 198 usart1: serial@f0020000 { 199 compatible = "atmel,at91sam9260-usart"; 200 reg = <0xf0020000 0x100>; 201 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; 202 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>, 203 <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 204 dma-names = "tx", "rx"; 205 pinctrl-names = "default"; 206 pinctrl-0 = <&pinctrl_usart1>; 207 clocks = <&usart1_clk>; 208 clock-names = "usart"; 209 status = "disabled"; 210 }; 211 212 uart0: serial@f0024000 { 213 compatible = "atmel,at91sam9260-usart"; 214 reg = <0xf0024000 0x100>; 215 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; 216 pinctrl-names = "default"; 217 pinctrl-0 = <&pinctrl_uart0>; 218 clocks = <&uart0_clk>; 219 clock-names = "usart"; 220 status = "disabled"; 221 }; 222 223 pwm0: pwm@f002c000 { 224 compatible = "atmel,sama5d3-pwm"; 225 reg = <0xf002c000 0x300>; 226 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>; 227 #pwm-cells = <3>; 228 clocks = <&pwm_clk>; 229 status = "disabled"; 230 }; 231 232 isi: isi@f0034000 { 233 compatible = "atmel,at91sam9g45-isi"; 234 reg = <0xf0034000 0x4000>; 235 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_isi_data_0_7>; 238 clocks = <&isi_clk>; 239 clock-names = "isi_clk"; 240 status = "disabled"; 241 }; 242 243 sfr: sfr@f0038000 { 244 compatible = "atmel,sama5d3-sfr", "syscon"; 245 reg = <0xf0038000 0x60>; 246 }; 247 248 mmc1: mmc@f8000000 { 249 compatible = "atmel,hsmci"; 250 reg = <0xf8000000 0x600>; 251 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>; 252 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>; 253 dma-names = "rxtx"; 254 pinctrl-names = "default"; 255 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; 256 status = "disabled"; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 clocks = <&mci1_clk>; 260 clock-names = "mci_clk"; 261 }; 262 263 spi1: spi@f8008000 { 264 #address-cells = <1>; 265 #size-cells = <0>; 266 compatible = "atmel,at91rm9200-spi"; 267 reg = <0xf8008000 0x100>; 268 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; 269 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>, 270 <&dma1 2 AT91_DMA_CFG_PER_ID(16)>; 271 dma-names = "tx", "rx"; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&pinctrl_spi1>; 274 clocks = <&spi1_clk>; 275 clock-names = "spi_clk"; 276 status = "disabled"; 277 }; 278 279 ssc1: ssc@f800c000 { 280 compatible = "atmel,at91sam9g45-ssc"; 281 reg = <0xf800c000 0x4000>; 282 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; 283 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>, 284 <&dma1 2 AT91_DMA_CFG_PER_ID(4)>; 285 dma-names = "tx", "rx"; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 288 clocks = <&ssc1_clk>; 289 clock-names = "pclk"; 290 status = "disabled"; 291 }; 292 293 adc0: adc@f8018000 { 294 #address-cells = <1>; 295 #size-cells = <0>; 296 compatible = "atmel,at91sam9x5-adc"; 297 reg = <0xf8018000 0x100>; 298 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; 299 pinctrl-names = "default"; 300 pinctrl-0 = < 301 &pinctrl_adc0_adtrg 302 &pinctrl_adc0_ad0 303 &pinctrl_adc0_ad1 304 &pinctrl_adc0_ad2 305 &pinctrl_adc0_ad3 306 &pinctrl_adc0_ad4 307 &pinctrl_adc0_ad5 308 &pinctrl_adc0_ad6 309 &pinctrl_adc0_ad7 310 &pinctrl_adc0_ad8 311 &pinctrl_adc0_ad9 312 &pinctrl_adc0_ad10 313 &pinctrl_adc0_ad11 314 >; 315 clocks = <&adc_clk>, 316 <&adc_op_clk>; 317 clock-names = "adc_clk", "adc_op_clk"; 318 atmel,adc-channels-used = <0xfff>; 319 atmel,adc-startup-time = <40>; 320 atmel,adc-use-external-triggers; 321 atmel,adc-vref = <3000>; 322 atmel,adc-res = <10 12>; 323 atmel,adc-sample-hold-time = <11>; 324 atmel,adc-res-names = "lowres", "highres"; 325 status = "disabled"; 326 327 trigger@0 { 328 reg = <0>; 329 trigger-name = "external-rising"; 330 trigger-value = <0x1>; 331 trigger-external; 332 }; 333 trigger@1 { 334 reg = <1>; 335 trigger-name = "external-falling"; 336 trigger-value = <0x2>; 337 trigger-external; 338 }; 339 trigger@2 { 340 reg = <2>; 341 trigger-name = "external-any"; 342 trigger-value = <0x3>; 343 trigger-external; 344 }; 345 trigger@3 { 346 reg = <3>; 347 trigger-name = "continuous"; 348 trigger-value = <0x6>; 349 }; 350 }; 351 352 i2c2: i2c@f801c000 { 353 compatible = "atmel,at91sam9x5-i2c"; 354 reg = <0xf801c000 0x4000>; 355 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>; 356 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, 357 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; 358 dma-names = "tx", "rx"; 359 pinctrl-names = "default"; 360 pinctrl-0 = <&pinctrl_i2c2>; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 clocks = <&twi2_clk>; 364 status = "disabled"; 365 }; 366 367 usart2: serial@f8020000 { 368 compatible = "atmel,at91sam9260-usart"; 369 reg = <0xf8020000 0x100>; 370 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 371 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>, 372 <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 373 dma-names = "tx", "rx"; 374 pinctrl-names = "default"; 375 pinctrl-0 = <&pinctrl_usart2>; 376 clocks = <&usart2_clk>; 377 clock-names = "usart"; 378 status = "disabled"; 379 }; 380 381 usart3: serial@f8024000 { 382 compatible = "atmel,at91sam9260-usart"; 383 reg = <0xf8024000 0x100>; 384 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; 385 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>, 386 <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 387 dma-names = "tx", "rx"; 388 pinctrl-names = "default"; 389 pinctrl-0 = <&pinctrl_usart3>; 390 clocks = <&usart3_clk>; 391 clock-names = "usart"; 392 status = "disabled"; 393 }; 394 395 sha@f8034000 { 396 compatible = "atmel,at91sam9g46-sha"; 397 reg = <0xf8034000 0x100>; 398 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; 399 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; 400 dma-names = "tx"; 401 clocks = <&sha_clk>; 402 clock-names = "sha_clk"; 403 }; 404 405 aes@f8038000 { 406 compatible = "atmel,at91sam9g46-aes"; 407 reg = <0xf8038000 0x100>; 408 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; 409 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, 410 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; 411 dma-names = "tx", "rx"; 412 clocks = <&aes_clk>; 413 clock-names = "aes_clk"; 414 }; 415 416 tdes@f803c000 { 417 compatible = "atmel,at91sam9g46-tdes"; 418 reg = <0xf803c000 0x100>; 419 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; 420 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, 421 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; 422 dma-names = "tx", "rx"; 423 clocks = <&tdes_clk>; 424 clock-names = "tdes_clk"; 425 }; 426 427 trng@f8040000 { 428 compatible = "atmel,at91sam9g45-trng"; 429 reg = <0xf8040000 0x100>; 430 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; 431 clocks = <&trng_clk>; 432 }; 433 434 dma0: dma-controller@ffffe600 { 435 compatible = "atmel,at91sam9g45-dma"; 436 reg = <0xffffe600 0x200>; 437 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; 438 #dma-cells = <2>; 439 clocks = <&dma0_clk>; 440 clock-names = "dma_clk"; 441 }; 442 443 dma1: dma-controller@ffffe800 { 444 compatible = "atmel,at91sam9g45-dma"; 445 reg = <0xffffe800 0x200>; 446 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 447 #dma-cells = <2>; 448 clocks = <&dma1_clk>; 449 clock-names = "dma_clk"; 450 }; 451 452 ramc0: ramc@ffffea00 { 453 compatible = "atmel,sama5d3-ddramc"; 454 reg = <0xffffea00 0x200>; 455 clocks = <&ddrck>, <&mpddr_clk>; 456 clock-names = "ddrck", "mpddr"; 457 }; 458 459 dbgu: serial@ffffee00 { 460 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 461 reg = <0xffffee00 0x200>; 462 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; 463 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>, 464 <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 465 dma-names = "tx", "rx"; 466 pinctrl-names = "default"; 467 pinctrl-0 = <&pinctrl_dbgu>; 468 clocks = <&dbgu_clk>; 469 clock-names = "usart"; 470 status = "disabled"; 471 }; 472 473 aic: interrupt-controller@fffff000 { 474 #interrupt-cells = <3>; 475 compatible = "atmel,sama5d3-aic"; 476 interrupt-controller; 477 reg = <0xfffff000 0x200>; 478 atmel,external-irqs = <47>; 479 }; 480 481 pinctrl@fffff200 { 482 bootph-all; 483 #address-cells = <1>; 484 #size-cells = <1>; 485 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; 486 ranges = <0xfffff200 0xfffff200 0xa00>; 487 atmel,mux-mask = < 488 /* A B C */ 489 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */ 490 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */ 491 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */ 492 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ 493 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ 494 >; 495 496 /* shared pinctrl settings */ 497 adc0 { 498 pinctrl_adc0_adtrg: adc0_adtrg { 499 atmel,pins = 500 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */ 501 }; 502 pinctrl_adc0_ad0: adc0_ad0 { 503 atmel,pins = 504 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */ 505 }; 506 pinctrl_adc0_ad1: adc0_ad1 { 507 atmel,pins = 508 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */ 509 }; 510 pinctrl_adc0_ad2: adc0_ad2 { 511 atmel,pins = 512 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */ 513 }; 514 pinctrl_adc0_ad3: adc0_ad3 { 515 atmel,pins = 516 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */ 517 }; 518 pinctrl_adc0_ad4: adc0_ad4 { 519 atmel,pins = 520 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */ 521 }; 522 pinctrl_adc0_ad5: adc0_ad5 { 523 atmel,pins = 524 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */ 525 }; 526 pinctrl_adc0_ad6: adc0_ad6 { 527 atmel,pins = 528 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */ 529 }; 530 pinctrl_adc0_ad7: adc0_ad7 { 531 atmel,pins = 532 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */ 533 }; 534 pinctrl_adc0_ad8: adc0_ad8 { 535 atmel,pins = 536 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */ 537 }; 538 pinctrl_adc0_ad9: adc0_ad9 { 539 atmel,pins = 540 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */ 541 }; 542 pinctrl_adc0_ad10: adc0_ad10 { 543 atmel,pins = 544 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */ 545 }; 546 pinctrl_adc0_ad11: adc0_ad11 { 547 atmel,pins = 548 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */ 549 }; 550 }; 551 552 dbgu { 553 bootph-all; 554 pinctrl_dbgu: dbgu-0 { 555 bootph-all; 556 atmel,pins = 557 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */ 558 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */ 559 }; 560 }; 561 562 i2c0 { 563 pinctrl_i2c0: i2c0-0 { 564 atmel,pins = 565 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ 566 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ 567 }; 568 }; 569 570 i2c1 { 571 pinctrl_i2c1: i2c1-0 { 572 atmel,pins = 573 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ 574 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ 575 }; 576 }; 577 578 i2c2 { 579 pinctrl_i2c2: i2c2-0 { 580 atmel,pins = 581 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */ 582 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */ 583 }; 584 }; 585 586 isi { 587 pinctrl_isi_data_0_7: isi-0-data-0-7 { 588 atmel,pins = 589 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ 590 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ 591 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ 592 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ 593 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ 594 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ 595 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ 596 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ 597 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ 598 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ 599 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ 600 }; 601 602 pinctrl_isi_data_8_9: isi-0-data-8-9 { 603 atmel,pins = 604 <AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ 605 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ 606 }; 607 608 pinctrl_isi_data_10_11: isi-0-data-10-11 { 609 atmel,pins = 610 <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC27 periph C ISI_PD10, conflicts with SPI1_NPCS2, TWCK1 */ 611 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC26 periph C ISI_PD11, conflicts with SPI1_NPCS1, TWD1 */ 612 }; 613 }; 614 615 mmc0 { 616 bootph-all; 617 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { 618 bootph-all; 619 atmel,pins = 620 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */ 621 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */ 622 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */ 623 }; 624 pinctrl_mmc0_dat1_3: mmc0_dat1_3 { 625 bootph-all; 626 atmel,pins = 627 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */ 628 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */ 629 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */ 630 }; 631 pinctrl_mmc0_dat4_7: mmc0_dat4_7 { 632 bootph-all; 633 atmel,pins = 634 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ 635 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ 636 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ 637 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ 638 }; 639 }; 640 641 mmc1 { 642 bootph-all; 643 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { 644 bootph-all; 645 atmel,pins = 646 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */ 647 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ 648 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ 649 }; 650 pinctrl_mmc1_dat1_3: mmc1_dat1_3 { 651 bootph-all; 652 atmel,pins = 653 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ 654 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ 655 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ 656 }; 657 }; 658 659 nand0 { 660 pinctrl_nand0_ale_cle: nand0_ale_cle-0 { 661 atmel,pins = 662 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */ 663 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */ 664 }; 665 }; 666 667 pwm0 { 668 pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 { 669 atmel,pins = 670 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */ 671 }; 672 pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 { 673 atmel,pins = 674 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */ 675 }; 676 pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 { 677 atmel,pins = 678 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */ 679 }; 680 pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 { 681 atmel,pins = 682 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX1 */ 683 }; 684 685 pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 { 686 atmel,pins = 687 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */ 688 }; 689 pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 { 690 atmel,pins = 691 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX0 */ 692 }; 693 pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 { 694 atmel,pins = 695 <AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */ 696 }; 697 pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 { 698 atmel,pins = 699 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */ 700 }; 701 pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 { 702 atmel,pins = 703 <AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX1 */ 704 }; 705 pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 { 706 atmel,pins = 707 <AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */ 708 }; 709 710 pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 { 711 atmel,pins = 712 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXCK */ 713 }; 714 pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 { 715 atmel,pins = 716 <AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA4 and TIOA0 */ 717 }; 718 pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 { 719 atmel,pins = 720 <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXEN */ 721 }; 722 pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 { 723 atmel,pins = 724 <AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA5 and TIOB0 */ 725 }; 726 727 pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 { 728 atmel,pins = 729 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */ 730 }; 731 pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 { 732 atmel,pins = 733 <AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA6 and TCLK0 */ 734 }; 735 pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 { 736 atmel,pins = 737 <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */ 738 }; 739 pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 { 740 atmel,pins = 741 <AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA7 */ 742 }; 743 }; 744 745 spi0 { 746 bootph-all; 747 pinctrl_spi0: spi0-0 { 748 bootph-all; 749 atmel,pins = 750 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */ 751 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */ 752 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */ 753 }; 754 }; 755 756 spi1 { 757 bootph-all; 758 pinctrl_spi1: spi1-0 { 759 bootph-all; 760 atmel,pins = 761 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */ 762 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */ 763 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */ 764 }; 765 }; 766 767 ssc0 { 768 pinctrl_ssc0_tx: ssc0_tx { 769 atmel,pins = 770 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */ 771 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */ 772 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */ 773 }; 774 775 pinctrl_ssc0_rx: ssc0_rx { 776 atmel,pins = 777 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */ 778 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */ 779 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */ 780 }; 781 }; 782 783 ssc1 { 784 pinctrl_ssc1_tx: ssc1_tx { 785 atmel,pins = 786 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */ 787 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */ 788 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */ 789 }; 790 791 pinctrl_ssc1_rx: ssc1_rx { 792 atmel,pins = 793 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */ 794 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */ 795 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */ 796 }; 797 }; 798 799 uart0 { 800 pinctrl_uart0: uart0-0 { 801 atmel,pins = 802 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* conflicts with PWMFI2, ISI_D8 */ 803 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with ISI_PCK */ 804 }; 805 }; 806 807 uart1 { 808 pinctrl_uart1: uart1-0 { 809 atmel,pins = 810 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* conflicts with TWD0, ISI_VSYNC */ 811 AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* conflicts with TWCK0, ISI_HSYNC */ 812 }; 813 }; 814 815 usart0 { 816 pinctrl_usart0: usart0-0 { 817 atmel,pins = 818 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */ 819 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */ 820 }; 821 822 pinctrl_usart0_rts_cts: usart0_rts_cts-0 { 823 atmel,pins = 824 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ 825 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ 826 }; 827 }; 828 829 usart1 { 830 pinctrl_usart1: usart1-0 { 831 atmel,pins = 832 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */ 833 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */ 834 }; 835 836 pinctrl_usart1_rts_cts: usart1_rts_cts-0 { 837 atmel,pins = 838 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */ 839 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */ 840 }; 841 }; 842 843 usart2 { 844 pinctrl_usart2: usart2-0 { 845 atmel,pins = 846 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */ 847 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */ 848 }; 849 850 pinctrl_usart2_rts_cts: usart2_rts_cts-0 { 851 atmel,pins = 852 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */ 853 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */ 854 }; 855 }; 856 857 usart3 { 858 pinctrl_usart3: usart3-0 { 859 atmel,pins = 860 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */ 861 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */ 862 }; 863 864 pinctrl_usart3_rts_cts: usart3_rts_cts-0 { 865 atmel,pins = 866 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */ 867 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */ 868 }; 869 }; 870 871 pioA: gpio@fffff200 { 872 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 873 reg = <0xfffff200 0x100>; 874 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; 875 #gpio-cells = <2>; 876 gpio-controller; 877 interrupt-controller; 878 #interrupt-cells = <2>; 879 clocks = <&pioA_clk>; 880 bootph-all; 881 }; 882 883 pioB: gpio@fffff400 { 884 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 885 reg = <0xfffff400 0x100>; 886 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; 887 #gpio-cells = <2>; 888 gpio-controller; 889 interrupt-controller; 890 #interrupt-cells = <2>; 891 clocks = <&pioB_clk>; 892 bootph-all; 893 }; 894 895 pioC: gpio@fffff600 { 896 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 897 reg = <0xfffff600 0x100>; 898 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; 899 #gpio-cells = <2>; 900 gpio-controller; 901 interrupt-controller; 902 #interrupt-cells = <2>; 903 clocks = <&pioC_clk>; 904 bootph-all; 905 }; 906 907 pioD: gpio@fffff800 { 908 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 909 reg = <0xfffff800 0x100>; 910 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; 911 #gpio-cells = <2>; 912 gpio-controller; 913 interrupt-controller; 914 #interrupt-cells = <2>; 915 clocks = <&pioD_clk>; 916 bootph-all; 917 }; 918 919 pioE: gpio@fffffa00 { 920 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 921 reg = <0xfffffa00 0x100>; 922 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; 923 #gpio-cells = <2>; 924 gpio-controller; 925 interrupt-controller; 926 #interrupt-cells = <2>; 927 clocks = <&pioE_clk>; 928 bootph-all; 929 }; 930 }; 931 932 pmc: pmc@fffffc00 { 933 compatible = "atmel,sama5d3-pmc", "syscon"; 934 reg = <0xfffffc00 0x120>; 935 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 936 interrupt-controller; 937 #address-cells = <1>; 938 #size-cells = <0>; 939 #interrupt-cells = <1>; 940 bootph-all; 941 942 main_rc_osc: main_rc_osc { 943 compatible = "atmel,at91sam9x5-clk-main-rc-osc"; 944 #clock-cells = <0>; 945 interrupt-parent = <&pmc>; 946 interrupts = <AT91_PMC_MOSCRCS>; 947 clock-frequency = <12000000>; 948 clock-accuracy = <50000000>; 949 }; 950 951 main_osc: main_osc { 952 compatible = "atmel,at91rm9200-clk-main-osc"; 953 #clock-cells = <0>; 954 interrupt-parent = <&pmc>; 955 interrupts = <AT91_PMC_MOSCS>; 956 clocks = <&main_xtal>; 957 }; 958 959 main: mainck { 960 compatible = "atmel,at91sam9x5-clk-main"; 961 #clock-cells = <0>; 962 interrupt-parent = <&pmc>; 963 interrupts = <AT91_PMC_MOSCSELS>; 964 clocks = <&main_rc_osc &main_osc>; 965 }; 966 967 plla: pllack@0 { 968 compatible = "atmel,sama5d3-clk-pll"; 969 #clock-cells = <0>; 970 interrupt-parent = <&pmc>; 971 interrupts = <AT91_PMC_LOCKA>; 972 clocks = <&main>; 973 reg = <0>; 974 atmel,clk-input-range = <8000000 50000000>; 975 #atmel,pll-clk-output-range-cells = <4>; 976 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>; 977 }; 978 979 plladiv: plladivck { 980 compatible = "atmel,at91sam9x5-clk-plldiv"; 981 #clock-cells = <0>; 982 clocks = <&plla>; 983 }; 984 985 utmi: utmick { 986 compatible = "atmel,at91sam9x5-clk-utmi"; 987 #clock-cells = <0>; 988 interrupt-parent = <&pmc>; 989 interrupts = <AT91_PMC_LOCKU>; 990 clocks = <&main>; 991 regmap-sfr = <&sfr>; 992 bootph-all; 993 }; 994 995 mck: masterck { 996 compatible = "atmel,at91sam9x5-clk-master"; 997 #clock-cells = <0>; 998 interrupt-parent = <&pmc>; 999 interrupts = <AT91_PMC_MCKRDY>; 1000 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; 1001 atmel,clk-output-range = <0 166000000>; 1002 atmel,clk-divisors = <1 2 4 3>; 1003 bootph-all; 1004 }; 1005 1006 usb: usbck { 1007 compatible = "atmel,at91sam9x5-clk-usb"; 1008 #clock-cells = <0>; 1009 clocks = <&plladiv>, <&utmi>; 1010 }; 1011 1012 prog: progck { 1013 compatible = "atmel,at91sam9x5-clk-programmable"; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 interrupt-parent = <&pmc>; 1017 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; 1018 1019 prog0: progck@0 { 1020 #clock-cells = <0>; 1021 reg = <0>; 1022 interrupts = <AT91_PMC_PCKRDY(0)>; 1023 }; 1024 1025 prog1: progck@1 { 1026 #clock-cells = <0>; 1027 reg = <1>; 1028 interrupts = <AT91_PMC_PCKRDY(1)>; 1029 }; 1030 1031 prog2: progck@2 { 1032 #clock-cells = <0>; 1033 reg = <2>; 1034 interrupts = <AT91_PMC_PCKRDY(2)>; 1035 }; 1036 }; 1037 1038 smd: smdclk { 1039 compatible = "atmel,at91sam9x5-clk-smd"; 1040 #clock-cells = <0>; 1041 clocks = <&plladiv>, <&utmi>; 1042 }; 1043 1044 systemck { 1045 compatible = "atmel,at91rm9200-clk-system"; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 1049 ddrck: ddrck@2 { 1050 #clock-cells = <0>; 1051 reg = <2>; 1052 clocks = <&mck>; 1053 }; 1054 1055 smdck: smdck@4 { 1056 #clock-cells = <0>; 1057 reg = <4>; 1058 clocks = <&smd>; 1059 }; 1060 1061 uhpck: uhpck@6 { 1062 #clock-cells = <0>; 1063 reg = <6>; 1064 clocks = <&usb>; 1065 }; 1066 1067 udpck: udpck@7 { 1068 #clock-cells = <0>; 1069 reg = <7>; 1070 clocks = <&usb>; 1071 }; 1072 1073 pck0: pck@8 { 1074 #clock-cells = <0>; 1075 reg = <8>; 1076 clocks = <&prog0>; 1077 }; 1078 1079 pck1: pck@9 { 1080 #clock-cells = <0>; 1081 reg = <9>; 1082 clocks = <&prog1>; 1083 }; 1084 1085 pck2: pck@10 { 1086 #clock-cells = <0>; 1087 reg = <10>; 1088 clocks = <&prog2>; 1089 }; 1090 }; 1091 1092 periphck { 1093 compatible = "atmel,at91sam9x5-clk-peripheral"; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 clocks = <&mck>; 1097 bootph-all; 1098 1099 dbgu_clk: dbgu_clk@2 { 1100 bootph-all; 1101 #clock-cells = <0>; 1102 reg = <2>; 1103 }; 1104 1105 hsmc_clk: hsmc_clk@5 { 1106 #clock-cells = <0>; 1107 reg = <5>; 1108 }; 1109 1110 pioA_clk: pioA_clk@6 { 1111 bootph-all; 1112 #clock-cells = <0>; 1113 reg = <6>; 1114 }; 1115 1116 pioB_clk: pioB_clk@7 { 1117 bootph-all; 1118 #clock-cells = <0>; 1119 reg = <7>; 1120 }; 1121 1122 pioC_clk: pioC_clk@8 { 1123 bootph-all; 1124 #clock-cells = <0>; 1125 reg = <8>; 1126 }; 1127 1128 pioD_clk: pioD_clk@9 { 1129 bootph-all; 1130 #clock-cells = <0>; 1131 reg = <9>; 1132 }; 1133 1134 pioE_clk: pioE_clk@10 { 1135 bootph-all; 1136 #clock-cells = <0>; 1137 reg = <10>; 1138 }; 1139 1140 usart0_clk: usart0_clk@12 { 1141 #clock-cells = <0>; 1142 reg = <12>; 1143 atmel,clk-output-range = <0 66000000>; 1144 }; 1145 1146 usart1_clk: usart1_clk@13 { 1147 #clock-cells = <0>; 1148 reg = <13>; 1149 atmel,clk-output-range = <0 66000000>; 1150 }; 1151 1152 usart2_clk: usart2_clk@14 { 1153 #clock-cells = <0>; 1154 reg = <14>; 1155 atmel,clk-output-range = <0 66000000>; 1156 }; 1157 1158 usart3_clk: usart3_clk@15 { 1159 #clock-cells = <0>; 1160 reg = <15>; 1161 atmel,clk-output-range = <0 66000000>; 1162 }; 1163 1164 uart0_clk: uart0_clk@16 { 1165 #clock-cells = <0>; 1166 reg = <16>; 1167 atmel,clk-output-range = <0 66000000>; 1168 }; 1169 1170 twi0_clk: twi0_clk@18 { 1171 reg = <18>; 1172 #clock-cells = <0>; 1173 atmel,clk-output-range = <0 16625000>; 1174 }; 1175 1176 twi1_clk: twi1_clk@19 { 1177 #clock-cells = <0>; 1178 reg = <19>; 1179 atmel,clk-output-range = <0 16625000>; 1180 }; 1181 1182 twi2_clk: twi2_clk@20 { 1183 #clock-cells = <0>; 1184 reg = <20>; 1185 atmel,clk-output-range = <0 16625000>; 1186 }; 1187 1188 mci0_clk: mci0_clk@21 { 1189 bootph-all; 1190 #clock-cells = <0>; 1191 reg = <21>; 1192 }; 1193 1194 mci1_clk: mci1_clk@22 { 1195 bootph-all; 1196 #clock-cells = <0>; 1197 reg = <22>; 1198 }; 1199 1200 spi0_clk: spi0_clk@24 { 1201 bootph-all; 1202 #clock-cells = <0>; 1203 reg = <24>; 1204 atmel,clk-output-range = <0 133000000>; 1205 }; 1206 1207 spi1_clk: spi1_clk@25 { 1208 bootph-all; 1209 #clock-cells = <0>; 1210 reg = <25>; 1211 atmel,clk-output-range = <0 133000000>; 1212 }; 1213 1214 tcb0_clk: tcb0_clk@26 { 1215 #clock-cells = <0>; 1216 reg = <26>; 1217 atmel,clk-output-range = <0 133000000>; 1218 }; 1219 1220 pwm_clk: pwm_clk@28 { 1221 #clock-cells = <0>; 1222 reg = <28>; 1223 }; 1224 1225 adc_clk: adc_clk@29 { 1226 #clock-cells = <0>; 1227 reg = <29>; 1228 atmel,clk-output-range = <0 66000000>; 1229 }; 1230 1231 dma0_clk: dma0_clk@30 { 1232 #clock-cells = <0>; 1233 reg = <30>; 1234 }; 1235 1236 dma1_clk: dma1_clk@31 { 1237 #clock-cells = <0>; 1238 reg = <31>; 1239 }; 1240 1241 uhphs_clk: uhphs_clk@32 { 1242 #clock-cells = <0>; 1243 reg = <32>; 1244 }; 1245 1246 udphs_clk: udphs_clk@33 { 1247 #clock-cells = <0>; 1248 reg = <33>; 1249 }; 1250 1251 isi_clk: isi_clk@37 { 1252 #clock-cells = <0>; 1253 reg = <37>; 1254 }; 1255 1256 ssc0_clk: ssc0_clk@38 { 1257 #clock-cells = <0>; 1258 reg = <38>; 1259 atmel,clk-output-range = <0 66000000>; 1260 }; 1261 1262 ssc1_clk: ssc1_clk@39 { 1263 #clock-cells = <0>; 1264 reg = <39>; 1265 atmel,clk-output-range = <0 66000000>; 1266 }; 1267 1268 sha_clk: sha_clk@42 { 1269 #clock-cells = <0>; 1270 reg = <42>; 1271 }; 1272 1273 aes_clk: aes_clk@43 { 1274 #clock-cells = <0>; 1275 reg = <43>; 1276 }; 1277 1278 tdes_clk: tdes_clk@44 { 1279 #clock-cells = <0>; 1280 reg = <44>; 1281 }; 1282 1283 trng_clk: trng_clk@45 { 1284 #clock-cells = <0>; 1285 reg = <45>; 1286 }; 1287 1288 fuse_clk: fuse_clk@48 { 1289 #clock-cells = <0>; 1290 reg = <48>; 1291 }; 1292 1293 mpddr_clk: mpddr_clk@49 { 1294 #clock-cells = <0>; 1295 reg = <49>; 1296 }; 1297 }; 1298 }; 1299 1300 rstc@fffffe00 { 1301 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; 1302 reg = <0xfffffe00 0x10>; 1303 clocks = <&clk32k>; 1304 }; 1305 1306 shutdown-controller@fffffe10 { 1307 compatible = "atmel,at91sam9x5-shdwc"; 1308 reg = <0xfffffe10 0x10>; 1309 clocks = <&clk32k>; 1310 }; 1311 1312 pit: timer@fffffe30 { 1313 compatible = "atmel,at91sam9260-pit"; 1314 reg = <0xfffffe30 0xf>; 1315 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 1316 clocks = <&mck>; 1317 bootph-all; 1318 }; 1319 1320 watchdog@fffffe40 { 1321 compatible = "atmel,at91sam9260-wdt"; 1322 reg = <0xfffffe40 0x10>; 1323 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; 1324 clocks = <&clk32k>; 1325 atmel,watchdog-type = "hardware"; 1326 atmel,reset-type = "all"; 1327 atmel,dbg-halt; 1328 status = "disabled"; 1329 }; 1330 1331 sckc@fffffe50 { 1332 compatible = "atmel,at91sam9x5-sckc"; 1333 reg = <0xfffffe50 0x4>; 1334 1335 slow_rc_osc: slow_rc_osc { 1336 compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; 1337 #clock-cells = <0>; 1338 clock-frequency = <32768>; 1339 clock-accuracy = <50000000>; 1340 atmel,startup-time-usec = <75>; 1341 }; 1342 1343 slow_osc: slow_osc { 1344 compatible = "atmel,at91sam9x5-clk-slow-osc"; 1345 #clock-cells = <0>; 1346 clocks = <&slow_xtal>; 1347 atmel,startup-time-usec = <1200000>; 1348 }; 1349 1350 clk32k: slowck { 1351 compatible = "atmel,at91sam9x5-clk-slow"; 1352 #clock-cells = <0>; 1353 clocks = <&slow_rc_osc &slow_osc>; 1354 }; 1355 }; 1356 1357 rtc@fffffeb0 { 1358 compatible = "atmel,at91rm9200-rtc"; 1359 reg = <0xfffffeb0 0x30>; 1360 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1361 clocks = <&clk32k>; 1362 }; 1363 }; 1364 1365 usb0: gadget@00500000 { 1366 #address-cells = <1>; 1367 #size-cells = <0>; 1368 compatible = "atmel,sama5d3-udc"; 1369 reg = <0x00500000 0x100000 1370 0xf8030000 0x4000>; 1371 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; 1372 clocks = <&udphs_clk>, <&utmi>; 1373 clock-names = "pclk", "hclk"; 1374 status = "disabled"; 1375 1376 ep0: endpoint@0 { 1377 reg = <0>; 1378 atmel,fifo-size = <64>; 1379 atmel,nb-banks = <1>; 1380 }; 1381 1382 ep1: endpoint@1 { 1383 reg = <1>; 1384 atmel,fifo-size = <1024>; 1385 atmel,nb-banks = <3>; 1386 atmel,can-dma; 1387 atmel,can-isoc; 1388 }; 1389 1390 ep2: endpoint@2 { 1391 reg = <2>; 1392 atmel,fifo-size = <1024>; 1393 atmel,nb-banks = <3>; 1394 atmel,can-dma; 1395 atmel,can-isoc; 1396 }; 1397 1398 ep3: endpoint@3 { 1399 reg = <3>; 1400 atmel,fifo-size = <1024>; 1401 atmel,nb-banks = <2>; 1402 atmel,can-dma; 1403 }; 1404 1405 ep4: endpoint@4 { 1406 reg = <4>; 1407 atmel,fifo-size = <1024>; 1408 atmel,nb-banks = <2>; 1409 atmel,can-dma; 1410 }; 1411 1412 ep5: endpoint@5 { 1413 reg = <5>; 1414 atmel,fifo-size = <1024>; 1415 atmel,nb-banks = <2>; 1416 atmel,can-dma; 1417 }; 1418 1419 ep6: endpoint@6 { 1420 reg = <6>; 1421 atmel,fifo-size = <1024>; 1422 atmel,nb-banks = <2>; 1423 atmel,can-dma; 1424 }; 1425 1426 ep7i: endpoint@7 { 1427 reg = <7>; 1428 atmel,fifo-size = <1024>; 1429 atmel,nb-banks = <2>; 1430 atmel,can-dma; 1431 }; 1432 1433 ep8: endpoint@8 { 1434 reg = <8>; 1435 atmel,fifo-size = <1024>; 1436 atmel,nb-banks = <2>; 1437 }; 1438 1439 ep9: endpoint@9 { 1440 reg = <9>; 1441 atmel,fifo-size = <1024>; 1442 atmel,nb-banks = <2>; 1443 }; 1444 1445 ep10: endpoint@a { 1446 reg = <10>; 1447 atmel,fifo-size = <1024>; 1448 atmel,nb-banks = <2>; 1449 }; 1450 1451 ep11: endpoint@b { 1452 reg = <11>; 1453 atmel,fifo-size = <1024>; 1454 atmel,nb-banks = <2>; 1455 }; 1456 1457 ep12: endpoint@c { 1458 reg = <12>; 1459 atmel,fifo-size = <1024>; 1460 atmel,nb-banks = <2>; 1461 }; 1462 1463 ep13: endpoint@d { 1464 reg = <13>; 1465 atmel,fifo-size = <1024>; 1466 atmel,nb-banks = <2>; 1467 }; 1468 1469 ep14: endpoint@e { 1470 reg = <14>; 1471 atmel,fifo-size = <1024>; 1472 atmel,nb-banks = <2>; 1473 }; 1474 1475 ep15: endpoint@f { 1476 reg = <15>; 1477 atmel,fifo-size = <1024>; 1478 atmel,nb-banks = <2>; 1479 }; 1480 }; 1481 1482 usb1: ohci@00600000 { 1483 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 1484 reg = <0x00600000 0x100000>; 1485 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; 1486 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; 1487 clock-names = "ohci_clk", "hclk", "uhpck"; 1488 status = "disabled"; 1489 }; 1490 1491 usb2: ehci@00700000 { 1492 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1493 reg = <0x00700000 0x100000>; 1494 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; 1495 clocks = <&utmi>, <&uhphs_clk>; 1496 clock-names = "usb_clk", "ehci_clk"; 1497 status = "disabled"; 1498 }; 1499 1500 nand0: nand@60000000 { 1501 compatible = "atmel,at91rm9200-nand"; 1502 #address-cells = <1>; 1503 #size-cells = <1>; 1504 ranges; 1505 reg = < 0x60000000 0x01000000 /* EBI CS3 */ 1506 0xffffc070 0x00000490 /* SMC PMECC regs */ 1507 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ 1508 0x00110000 0x00018000 /* ROM code */ 1509 >; 1510 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; 1511 atmel,nand-addr-offset = <21>; 1512 atmel,nand-cmd-offset = <22>; 1513 atmel,nand-has-dma; 1514 pinctrl-names = "default"; 1515 pinctrl-0 = <&pinctrl_nand0_ale_cle>; 1516 atmel,pmecc-lookup-table-offset = <0x0 0x8000>; 1517 status = "disabled"; 1518 1519 nfc@70000000 { 1520 compatible = "atmel,sama5d3-nfc"; 1521 #address-cells = <1>; 1522 #size-cells = <1>; 1523 reg = < 1524 0x70000000 0x08000000 /* NFC Command Registers */ 1525 0xffffc000 0x00000070 /* NFC HSMC regs */ 1526 0x00200000 0x00100000 /* NFC SRAM banks */ 1527 >; 1528 clocks = <&hsmc_clk>; 1529 }; 1530 }; 1531 }; 1532 1533 onewire_tm: onewire { 1534 compatible = "w1-gpio"; 1535 status = "disabled"; 1536 }; 1537}; 1538