1// SPDX-License-Identifier: GPL-2.0+
2
3#include <dt-bindings/memory/stm32-sdram.h>
4/{
5	soc {
6		bootph-all;
7
8		fmc: fmc@A0000000 {
9			compatible = "st,stm32-fmc";
10			reg = <0xa0000000 0x1000>;
11			clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
12			pinctrl-0 = <&fmc_pins>;
13			pinctrl-names = "default";
14			status = "okay";
15			bootph-all;
16		};
17
18		mac: ethernet@40028000 {
19			compatible = "st,stm32-dwmac";
20			reg = <0x40028000 0x8000>;
21			reg-names = "stmmaceth";
22			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
23				 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
24				 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
25			interrupts = <61>, <62>;
26			interrupt-names = "macirq", "eth_wake_irq";
27			snps,pbl = <8>;
28			snps,mixed-burst;
29			pinctrl-0 = <&ethernet_mii>;
30			phy-mode = "rmii";
31			phy-handle = <&phy0>;
32
33			status = "okay";
34
35			mdio0 {
36				#address-cells = <1>;
37				#size-cells = <0>;
38				compatible = "snps,dwmac-mdio";
39				phy0: ethernet-phy@0 {
40					reg = <0>;
41				};
42			};
43		};
44
45		qspi: spi@A0001000 {
46			compatible = "st,stm32f469-qspi";
47			#address-cells = <1>;
48			#size-cells = <0>;
49			reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
50			reg-names = "qspi", "qspi_mm";
51			interrupts = <92>;
52			spi-max-frequency = <108000000>;
53			clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
54			resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
55			pinctrl-0 = <&qspi_pins>;
56
57			status = "okay";
58		};
59	};
60};
61
62&clk_hse {
63	bootph-all;
64};
65
66&gpioa {
67	bootph-all;
68};
69
70&gpiob {
71	bootph-all;
72};
73
74&gpioc {
75	bootph-all;
76};
77
78&gpiod {
79	bootph-all;
80};
81
82&gpioe {
83	bootph-all;
84};
85
86&gpiof {
87	bootph-all;
88};
89
90&gpiog {
91	bootph-all;
92};
93
94&gpioh {
95	bootph-all;
96};
97
98&gpioi {
99	bootph-all;
100};
101
102&pinctrl {
103	bootph-all;
104
105	fmc_pins: fmc@0 {
106		bootph-all;
107		pins
108		{
109		 bootph-all;
110		};
111	};
112};
113
114&pwrcfg {
115	bootph-all;
116};
117
118&rcc {
119	bootph-all;
120};
121
122&timers5 {
123	bootph-all;
124};
125
126&usart1 {
127	bootph-all;
128	clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
129};
130