1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/input/input.h> 5#include "tegra30.dtsi" 6 7/ { 8 model = "Pegatron Chagall"; 9 compatible = "pegatron,chagall", "nvidia,tegra30"; 10 11 chosen { 12 stdout-path = &uarta; 13 }; 14 15 aliases { 16 i2c0 = &pwr_i2c; 17 18 mmc0 = &sdmmc4; /* eMMC */ 19 mmc1 = &sdmmc1; /* uSD slot */ 20 21 rtc0 = &pmic; 22 rtc1 = "/rtc@7000e000"; 23 24 usb0 = &usb1; 25 usb1 = &usb3; /* Dock USB */ 26 }; 27 28 memory { 29 device_type = "memory"; 30 reg = <0x80000000 0x40000000>; 31 }; 32 33 host1x@50000000 { 34 dc@54200000 { 35 rgb { 36 status = "okay"; 37 38 port { 39 dpi_output: endpoint { 40 remote-endpoint = <&bridge_input>; 41 bus-width = <24>; 42 }; 43 }; 44 }; 45 }; 46 }; 47 48 pinmux@70000868 { 49 pinctrl-names = "default"; 50 pinctrl-0 = <&state_default>; 51 52 state_default: pinmux { 53 /* SDMMC1 pinmux */ 54 sdmmc1_clk_pz0 { 55 nvidia,pins = "sdmmc1_clk_pz0"; 56 nvidia,function = "sdmmc1"; 57 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 58 nvidia,tristate = <TEGRA_PIN_DISABLE>; 59 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 60 }; 61 62 sdmmc1_dat3_py4 { 63 nvidia,pins = "sdmmc1_dat3_py4", 64 "sdmmc1_dat2_py5", 65 "sdmmc1_dat1_py6", 66 "sdmmc1_dat0_py7", 67 "sdmmc1_cmd_pz1"; 68 nvidia,function = "sdmmc1"; 69 nvidia,pull = <TEGRA_PIN_PULL_UP>; 70 nvidia,tristate = <TEGRA_PIN_DISABLE>; 71 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 72 }; 73 74 /* SDMMC2 pinmux */ 75 vi_d1_pd5 { 76 nvidia,pins = "vi_d1_pd5", 77 "vi_d2_pl0", 78 "vi_d3_pl1", 79 "vi_d5_pl3", 80 "vi_d7_pl5"; 81 nvidia,function = "sdmmc2"; 82 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 83 nvidia,tristate = <TEGRA_PIN_DISABLE>; 84 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 85 }; 86 87 vi_d8_pl6 { 88 nvidia,pins = "vi_d8_pl6", 89 "vi_d9_pl7"; 90 nvidia,function = "sdmmc2"; 91 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 92 nvidia,tristate = <TEGRA_PIN_DISABLE>; 93 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 94 nvidia,lock = <0>; 95 nvidia,io-reset = <0>; 96 }; 97 98 /* SDMMC3 pinmux */ 99 sdmmc3_clk_pa6 { 100 nvidia,pins = "sdmmc3_clk_pa6"; 101 nvidia,function = "sdmmc3"; 102 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 103 nvidia,tristate = <TEGRA_PIN_DISABLE>; 104 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 105 }; 106 107 sdmmc3_cmd_pa7 { 108 nvidia,pins = "sdmmc3_cmd_pa7", 109 "sdmmc3_dat3_pb4", 110 "sdmmc3_dat2_pb5", 111 "sdmmc3_dat1_pb6", 112 "sdmmc3_dat0_pb7", 113 "sdmmc3_dat5_pd0", 114 "sdmmc3_dat4_pd1", 115 "sdmmc3_dat6_pd3", 116 "sdmmc3_dat7_pd4"; 117 nvidia,function = "sdmmc3"; 118 nvidia,pull = <TEGRA_PIN_PULL_UP>; 119 nvidia,tristate = <TEGRA_PIN_DISABLE>; 120 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 121 }; 122 123 /* SDMMC4 pinmux */ 124 sdmmc4_clk_pcc4 { 125 nvidia,pins = "sdmmc4_clk_pcc4"; 126 nvidia,function = "sdmmc4"; 127 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 128 nvidia,tristate = <TEGRA_PIN_DISABLE>; 129 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 130 }; 131 132 sdmmc4_cmd_pt7 { 133 nvidia,pins = "sdmmc4_cmd_pt7", 134 "sdmmc4_dat0_paa0", 135 "sdmmc4_dat1_paa1", 136 "sdmmc4_dat2_paa2", 137 "sdmmc4_dat3_paa3", 138 "sdmmc4_dat4_paa4", 139 "sdmmc4_dat5_paa5", 140 "sdmmc4_dat6_paa6", 141 "sdmmc4_dat7_paa7"; 142 nvidia,function = "sdmmc4"; 143 nvidia,pull = <TEGRA_PIN_PULL_UP>; 144 nvidia,tristate = <TEGRA_PIN_DISABLE>; 145 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 146 }; 147 148 /* I2C pinmux */ 149 gen1_i2c_scl_pc4 { 150 nvidia,pins = "gen1_i2c_scl_pc4", 151 "gen1_i2c_sda_pc5"; 152 nvidia,function = "i2c1"; 153 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 154 nvidia,tristate = <TEGRA_PIN_DISABLE>; 155 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 156 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 157 nvidia,lock = <0>; 158 }; 159 160 gen2_i2c_scl_pt5 { 161 nvidia,pins = "gen2_i2c_scl_pt5", 162 "gen2_i2c_sda_pt6"; 163 nvidia,function = "i2c2"; 164 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 165 nvidia,tristate = <TEGRA_PIN_DISABLE>; 166 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 167 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 168 nvidia,lock = <0>; 169 }; 170 171 cam_i2c_scl_pbb1 { 172 nvidia,pins = "cam_i2c_scl_pbb1", 173 "cam_i2c_sda_pbb2"; 174 nvidia,function = "i2c3"; 175 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 176 nvidia,tristate = <TEGRA_PIN_DISABLE>; 177 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 178 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 179 nvidia,lock = <0>; 180 }; 181 182 ddc_scl_pv4 { 183 nvidia,pins = "ddc_scl_pv4", 184 "ddc_sda_pv5"; 185 nvidia,function = "i2c4"; 186 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 187 nvidia,tristate = <TEGRA_PIN_DISABLE>; 188 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 189 nvidia,lock = <0>; 190 }; 191 192 pwr_i2c_scl_pz6 { 193 nvidia,pins = "pwr_i2c_scl_pz6", 194 "pwr_i2c_sda_pz7"; 195 nvidia,function = "i2cpwr"; 196 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 197 nvidia,tristate = <TEGRA_PIN_DISABLE>; 198 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 199 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 200 nvidia,lock = <0>; 201 }; 202 203 /* HDMI-CEC pinmux */ 204 hdmi_cec_pee3 { 205 nvidia,pins = "hdmi_cec_pee3"; 206 nvidia,function = "cec"; 207 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 208 nvidia,tristate = <TEGRA_PIN_DISABLE>; 209 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 210 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 211 nvidia,lock = <0>; 212 }; 213 214 /* UART-A */ 215 ulpi_data0_po1 { 216 nvidia,pins = "ulpi_data0_po1"; 217 nvidia,function = "uarta"; 218 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 219 nvidia,tristate = <TEGRA_PIN_DISABLE>; 220 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 221 }; 222 223 ulpi_data1_po2 { 224 nvidia,pins = "ulpi_data1_po2", 225 "ulpi_data2_po3", 226 "ulpi_data3_po4", 227 "ulpi_data4_po5", 228 "ulpi_data5_po6", 229 "ulpi_data6_po7"; 230 nvidia,function = "uarta"; 231 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 232 nvidia,tristate = <TEGRA_PIN_DISABLE>; 233 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 234 }; 235 236 ulpi_data7_po0 { 237 nvidia,pins = "ulpi_data7_po0"; 238 nvidia,function = "uarta"; 239 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 240 nvidia,tristate = <TEGRA_PIN_DISABLE>; 241 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 242 }; 243 244 /* UART-B */ 245 uart2_txd_pc2 { 246 nvidia,pins = "uart2_txd_pc2", 247 "uart2_rts_n_pj6"; 248 nvidia,function = "uartb"; 249 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 250 nvidia,tristate = <TEGRA_PIN_DISABLE>; 251 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 252 }; 253 254 uart2_rxd_pc3 { 255 nvidia,pins = "uart2_rxd_pc3", 256 "uart2_cts_n_pj5"; 257 nvidia,function = "uartb"; 258 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 259 nvidia,tristate = <TEGRA_PIN_DISABLE>; 260 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 261 }; 262 263 /* UART-C */ 264 uart3_cts_n_pa1 { 265 nvidia,pins = "uart3_cts_n_pa1", 266 "uart3_rxd_pw7"; 267 nvidia,function = "uartc"; 268 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 269 nvidia,tristate = <TEGRA_PIN_DISABLE>; 270 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 271 }; 272 273 uart3_rts_n_pc0 { 274 nvidia,pins = "uart3_rts_n_pc0", 275 "uart3_txd_pw6"; 276 nvidia,function = "uartc"; 277 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 278 nvidia,tristate = <TEGRA_PIN_DISABLE>; 279 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 280 }; 281 282 /* UART-D */ 283 ulpi_clk_py0 { 284 nvidia,pins = "ulpi_clk_py0", 285 "ulpi_stp_py3"; 286 nvidia,function = "uartd"; 287 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 288 nvidia,tristate = <TEGRA_PIN_DISABLE>; 289 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 290 }; 291 292 ulpi_dir_py1 { 293 nvidia,pins = "ulpi_dir_py1", 294 "ulpi_nxt_py2"; 295 nvidia,function = "uartd"; 296 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 297 nvidia,tristate = <TEGRA_PIN_DISABLE>; 298 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 299 }; 300 301 /* I2S pinmux */ 302 dap1_fs_pn0 { 303 nvidia,pins = "dap1_fs_pn0", 304 "dap1_din_pn1", 305 "dap1_dout_pn2", 306 "dap1_sclk_pn3"; 307 nvidia,function = "i2s0"; 308 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 309 nvidia,tristate = <TEGRA_PIN_DISABLE>; 310 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 311 }; 312 313 dap2_fs_pa2 { 314 nvidia,pins = "dap2_fs_pa2", 315 "dap2_sclk_pa3", 316 "dap2_din_pa4", 317 "dap2_dout_pa5"; 318 nvidia,function = "i2s1"; 319 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 320 nvidia,tristate = <TEGRA_PIN_DISABLE>; 321 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 322 }; 323 324 dap3_fs_pp0 { 325 nvidia,pins = "dap3_fs_pp0", 326 "dap3_din_pp1", 327 "dap3_dout_pp2", 328 "dap3_sclk_pp3"; 329 nvidia,function = "i2s2"; 330 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 331 nvidia,tristate = <TEGRA_PIN_DISABLE>; 332 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 333 }; 334 335 dap4_fs_pp4 { 336 nvidia,pins = "dap4_fs_pp4", 337 "dap4_din_pp5", 338 "dap4_dout_pp6", 339 "dap4_sclk_pp7"; 340 nvidia,function = "i2s3"; 341 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 342 nvidia,tristate = <TEGRA_PIN_DISABLE>; 343 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 344 }; 345 346 pcc2 { 347 nvidia,pins = "pcc2"; 348 nvidia,function = "i2s4"; 349 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 350 nvidia,tristate = <TEGRA_PIN_DISABLE>; 351 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 352 }; 353 354 /* PCI-e pinmux */ 355 pex_l2_rst_n_pcc6 { 356 nvidia,pins = "pex_l2_rst_n_pcc6", 357 "pex_l0_rst_n_pdd1", 358 "pex_l1_rst_n_pdd5"; 359 nvidia,function = "pcie"; 360 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 361 nvidia,tristate = <TEGRA_PIN_DISABLE>; 362 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 363 }; 364 365 pex_l2_clkreq_n_pcc7 { 366 nvidia,pins = "pex_l2_clkreq_n_pcc7", 367 "pex_l0_prsnt_n_pdd0", 368 "pex_l0_clkreq_n_pdd2", 369 "pex_l2_prsnt_n_pdd7"; 370 nvidia,function = "pcie"; 371 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 372 nvidia,tristate = <TEGRA_PIN_DISABLE>; 373 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 374 }; 375 376 pex_wake_n_pdd3 { 377 nvidia,pins = "pex_wake_n_pdd3"; 378 nvidia,function = "pcie"; 379 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 380 nvidia,tristate = <TEGRA_PIN_DISABLE>; 381 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 382 }; 383 384 /* SPI pinmux */ 385 spi1_mosi_px4 { 386 nvidia,pins = "spi1_mosi_px4", 387 "spi1_sck_px5", 388 "spi1_cs0_n_px6", 389 "spi1_miso_px7"; 390 nvidia,function = "spi1"; 391 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 392 nvidia,tristate = <TEGRA_PIN_DISABLE>; 393 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 394 }; 395 396 spi2_cs1_n_pw2 { 397 nvidia,pins = "spi2_cs1_n_pw2", 398 "spi2_cs2_n_pw3"; 399 nvidia,function = "spi2"; 400 nvidia,pull = <TEGRA_PIN_PULL_UP>; 401 nvidia,tristate = <TEGRA_PIN_DISABLE>; 402 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 403 }; 404 405 spi2_sck_px2 { 406 nvidia,pins = "spi2_sck_px2"; 407 nvidia,function = "gmi"; 408 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 409 nvidia,tristate = <TEGRA_PIN_DISABLE>; 410 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 411 }; 412 413 gmi_a16_pj7 { 414 nvidia,pins = "gmi_a16_pj7", 415 "gmi_a19_pk7"; 416 nvidia,function = "spi4"; 417 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 418 nvidia,tristate = <TEGRA_PIN_DISABLE>; 419 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 420 }; 421 422 gmi_a17_pb0 { 423 nvidia,pins = "gmi_a17_pb0", 424 "gmi_a18_pb1"; 425 nvidia,function = "spi4"; 426 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 427 nvidia,tristate = <TEGRA_PIN_DISABLE>; 428 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 429 }; 430 431 spi2_mosi_px0 { 432 nvidia,pins = "spi2_mosi_px0"; 433 nvidia,function = "spi6"; 434 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 435 nvidia,tristate = <TEGRA_PIN_DISABLE>; 436 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 437 }; 438 439 spdif_out_pk5 { 440 nvidia,pins = "spdif_out_pk5"; 441 nvidia,function = "spdif"; 442 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 443 nvidia,tristate = <TEGRA_PIN_DISABLE>; 444 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 445 }; 446 447 spdif_in_pk6 { 448 nvidia,pins = "spdif_in_pk6"; 449 nvidia,function = "spdif"; 450 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 451 nvidia,tristate = <TEGRA_PIN_DISABLE>; 452 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 453 }; 454 455 /* Display A pinmux */ 456 lcd_pwr0_pb2 { 457 nvidia,pins = "lcd_pwr0_pb2", 458 "lcd_pclk_pb3", 459 "lcd_pwr1_pc1", 460 "lcd_pwr2_pc6", 461 "lcd_d0_pe0", 462 "lcd_d1_pe1", 463 "lcd_d2_pe2", 464 "lcd_d3_pe3", 465 "lcd_d4_pe4", 466 "lcd_d5_pe5", 467 "lcd_d6_pe6", 468 "lcd_d7_pe7", 469 "lcd_d8_pf0", 470 "lcd_d9_pf1", 471 "lcd_d10_pf2", 472 "lcd_d11_pf3", 473 "lcd_d12_pf4", 474 "lcd_d13_pf5", 475 "lcd_d14_pf6", 476 "lcd_d15_pf7", 477 "lcd_de_pj1", 478 "lcd_hsync_pj3", 479 "lcd_vsync_pj4", 480 "lcd_d16_pm0", 481 "lcd_d17_pm1", 482 "lcd_d18_pm2", 483 "lcd_d19_pm3", 484 "lcd_d20_pm4", 485 "lcd_d21_pm5", 486 "lcd_d22_pm6", 487 "lcd_d23_pm7", 488 "lcd_cs0_n_pn4", 489 "lcd_sdout_pn5", 490 "lcd_dc0_pn6", 491 "lcd_sdin_pz2", 492 "lcd_wr_n_pz3", 493 "lcd_sck_pz4", 494 "lcd_cs1_n_pw0", 495 "lcd_m1_pw1"; 496 nvidia,function = "displaya"; 497 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 498 nvidia,tristate = <TEGRA_PIN_DISABLE>; 499 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 500 }; 501 502 lcd_dc1_pd2 { 503 nvidia,pins = "lcd_dc1_pd2"; 504 nvidia,function = "displaya"; 505 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 506 nvidia,tristate = <TEGRA_PIN_DISABLE>; 507 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 508 }; 509 510 clk_32k_out_pa0 { 511 nvidia,pins = "clk_32k_out_pa0"; 512 nvidia,function = "blink"; 513 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 514 nvidia,tristate = <TEGRA_PIN_DISABLE>; 515 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 516 }; 517 518 /* KBC keys */ 519 kb_row0_pr0 { 520 nvidia,pins = "kb_row0_pr0", 521 "kb_row1_pr1", 522 "kb_row2_pr2", 523 "kb_row3_pr3", 524 "kb_row8_ps0", 525 "kb_col0_pq0", 526 "kb_col1_pq1", 527 "kb_col2_pq2", 528 "kb_col3_pq3", 529 "kb_col4_pq4", 530 "kb_col5_pq5", 531 "kb_col7_pq7"; 532 nvidia,function = "kbc"; 533 nvidia,pull = <TEGRA_PIN_PULL_UP>; 534 nvidia,tristate = <TEGRA_PIN_DISABLE>; 535 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 536 }; 537 538 kb_row4_pr4 { 539 nvidia,pins = "kb_row4_pr4", 540 "kb_row7_pr7", 541 "kb_row10_ps2", 542 "kb_row13_ps5"; 543 nvidia,function = "kbc"; 544 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 545 nvidia,tristate = <TEGRA_PIN_DISABLE>; 546 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 547 }; 548 549 kb_row11_ps3 { 550 nvidia,pins = "kb_row11_ps3", 551 "kb_row12_ps4", 552 "kb_row15_ps7"; 553 nvidia,function = "kbc"; 554 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 555 nvidia,tristate = <TEGRA_PIN_DISABLE>; 556 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 557 }; 558 559 kb_row14_ps6 { 560 nvidia,pins = "kb_row14_ps6"; 561 nvidia,function = "kbc"; 562 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 563 nvidia,tristate = <TEGRA_PIN_DISABLE>; 564 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 565 }; 566 567 gmi_iordy_pi5 { 568 nvidia,pins = "gmi_iordy_pi5"; 569 nvidia,function = "rsvd1"; 570 nvidia,pull = <TEGRA_PIN_PULL_UP>; 571 nvidia,tristate = <TEGRA_PIN_DISABLE>; 572 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 573 }; 574 575 vi_pclk_pt0 { 576 nvidia,pins = "vi_pclk_pt0"; 577 nvidia,function = "rsvd1"; 578 nvidia,pull = <TEGRA_PIN_PULL_UP>; 579 nvidia,tristate = <TEGRA_PIN_ENABLE>; 580 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 581 nvidia,lock = <0>; 582 nvidia,io-reset = <0>; 583 }; 584 585 pu1 { 586 nvidia,pins = "pu1"; 587 nvidia,function = "rsvd1"; 588 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 589 nvidia,tristate = <TEGRA_PIN_DISABLE>; 590 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 591 }; 592 593 pu2 { 594 nvidia,pins = "pu2"; 595 nvidia,function = "rsvd1"; 596 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 597 nvidia,tristate = <TEGRA_PIN_DISABLE>; 598 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 599 }; 600 601 pv0 { 602 nvidia,pins = "pv0"; 603 nvidia,function = "rsvd1"; 604 nvidia,pull = <TEGRA_PIN_PULL_UP>; 605 nvidia,tristate = <TEGRA_PIN_DISABLE>; 606 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 607 }; 608 609 pv1 { 610 nvidia,pins = "pv1"; 611 nvidia,function = "rsvd1"; 612 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 613 nvidia,tristate = <TEGRA_PIN_DISABLE>; 614 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 615 }; 616 617 pcc1 { 618 nvidia,pins = "pcc1"; 619 nvidia,function = "rsvd2"; 620 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 621 nvidia,tristate = <TEGRA_PIN_DISABLE>; 622 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 623 }; 624 625 sdmmc4_rst_n_pcc3 { 626 nvidia,pins = "sdmmc4_rst_n_pcc3"; 627 nvidia,function = "rsvd2"; 628 nvidia,pull = <TEGRA_PIN_PULL_UP>; 629 nvidia,tristate = <TEGRA_PIN_DISABLE>; 630 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 631 }; 632 633 pv3 { 634 nvidia,pins = "pv3"; 635 nvidia,function = "rsvd2"; 636 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 637 nvidia,tristate = <TEGRA_PIN_DISABLE>; 638 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 639 }; 640 641 vi_vsync_pd6 { 642 nvidia,pins = "vi_vsync_pd6", 643 "vi_hsync_pd7"; 644 nvidia,function = "rsvd2"; 645 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 646 nvidia,tristate = <TEGRA_PIN_DISABLE>; 647 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 648 nvidia,lock = <0>; 649 nvidia,io-reset = <0>; 650 }; 651 652 vi_d10_pt2 { 653 nvidia,pins = "vi_d10_pt2", 654 "vi_d0_pt4", "pbb0"; 655 nvidia,function = "rsvd2"; 656 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 657 nvidia,tristate = <TEGRA_PIN_DISABLE>; 658 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 659 }; 660 661 vi_d11_pt3 { 662 nvidia,pins = "vi_d11_pt3"; 663 nvidia,function = "rsvd2"; 664 nvidia,pull = <TEGRA_PIN_PULL_UP>; 665 nvidia,tristate = <TEGRA_PIN_DISABLE>; 666 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 667 }; 668 669 pu0 { 670 nvidia,pins = "pu0"; 671 nvidia,function = "rsvd4"; 672 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 673 nvidia,tristate = <TEGRA_PIN_DISABLE>; 674 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 675 }; 676 677 pu3 { 678 nvidia,pins = "pu3"; 679 nvidia,function = "rsvd4"; 680 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 681 nvidia,tristate = <TEGRA_PIN_DISABLE>; 682 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 683 }; 684 685 pu6 { 686 nvidia,pins = "pu6"; 687 nvidia,function = "rsvd4"; 688 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 689 nvidia,tristate = <TEGRA_PIN_DISABLE>; 690 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 691 }; 692 693 pex_l1_prsnt_n_pdd4 { 694 nvidia,pins = "pex_l1_prsnt_n_pdd4", 695 "pex_l1_clkreq_n_pdd6"; 696 nvidia,function = "rsvd4"; 697 nvidia,pull = <TEGRA_PIN_PULL_UP>; 698 nvidia,tristate = <TEGRA_PIN_ENABLE>; 699 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 700 }; 701 702 gmi_wait_pi7 { 703 nvidia,pins = "gmi_wait_pi7", 704 "gmi_cs0_n_pj0", 705 "gmi_cs1_n_pj2", 706 "gmi_cs4_n_pk2"; 707 nvidia,function = "nand"; 708 nvidia,pull = <TEGRA_PIN_PULL_UP>; 709 nvidia,tristate = <TEGRA_PIN_ENABLE>; 710 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 711 }; 712 713 gmi_ad0_pg0 { 714 nvidia,pins = "gmi_ad0_pg0", 715 "gmi_ad1_pg1", 716 "gmi_ad2_pg2", 717 "gmi_ad3_pg3", 718 "gmi_ad4_pg4", 719 "gmi_ad5_pg5", 720 "gmi_ad6_pg6", 721 "gmi_ad7_pg7", 722 "gmi_wr_n_pi0", 723 "gmi_oe_n_pi1", 724 "gmi_dqs_pi2", 725 "gmi_adv_n_pk0", 726 "gmi_clk_pk1"; 727 nvidia,function = "nand"; 728 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 729 nvidia,tristate = <TEGRA_PIN_ENABLE>; 730 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 731 }; 732 733 gmi_cs2_n_pk3 { 734 nvidia,pins = "gmi_cs2_n_pk3"; 735 nvidia,function = "rsvd1"; 736 nvidia,pull = <TEGRA_PIN_PULL_UP>; 737 nvidia,tristate = <TEGRA_PIN_DISABLE>; 738 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 739 }; 740 741 gmi_cs3_n_pk4 { 742 nvidia,pins = "gmi_cs3_n_pk4"; 743 nvidia,function = "nand"; 744 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 745 nvidia,tristate = <TEGRA_PIN_DISABLE>; 746 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 747 }; 748 749 gmi_ad10_ph2 { 750 nvidia,pins = "gmi_ad10_ph2", 751 "gmi_ad11_ph3", 752 "gmi_ad14_ph6"; 753 nvidia,function = "nand"; 754 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 755 nvidia,tristate = <TEGRA_PIN_DISABLE>; 756 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 757 }; 758 759 gmi_ad13_ph5 { 760 nvidia,pins = "gmi_ad13_ph5", 761 "gmi_ad12_ph4", 762 "gmi_cs7_n_pi6"; 763 nvidia,function = "nand"; 764 nvidia,pull = <TEGRA_PIN_PULL_UP>; 765 nvidia,tristate = <TEGRA_PIN_DISABLE>; 766 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 767 }; 768 769 gmi_rst_n_pi4 { 770 nvidia,pins = "gmi_rst_n_pi4"; 771 nvidia,function = "gmi"; 772 nvidia,pull = <TEGRA_PIN_PULL_UP>; 773 nvidia,tristate = <TEGRA_PIN_DISABLE>; 774 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 775 }; 776 777 gmi_ad8_ph0 { 778 nvidia,pins = "gmi_ad8_ph0"; 779 nvidia,function = "pwm0"; 780 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 781 nvidia,tristate = <TEGRA_PIN_DISABLE>; 782 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 783 }; 784 785 gmi_ad9_ph1 { 786 nvidia,pins = "gmi_ad9_ph1"; 787 nvidia,function = "pwm1"; 788 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 789 nvidia,tristate = <TEGRA_PIN_DISABLE>; 790 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 791 }; 792 793 gmi_wp_n_pc7 { 794 nvidia,pins = "gmi_wp_n_pc7"; 795 nvidia,function = "gmi"; 796 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 797 nvidia,tristate = <TEGRA_PIN_DISABLE>; 798 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 799 }; 800 801 gmi_cs6_n_pi3 { 802 nvidia,pins = "gmi_cs6_n_pi3"; 803 nvidia,function = "sata"; 804 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 805 nvidia,tristate = <TEGRA_PIN_DISABLE>; 806 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 807 }; 808 809 vi_d4_pl2 { 810 nvidia,pins = "vi_d4_pl2"; 811 nvidia,function = "vi"; 812 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 813 nvidia,tristate = <TEGRA_PIN_DISABLE>; 814 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 815 }; 816 817 vi_d6_pl4 { 818 nvidia,pins = "vi_d6_pl4"; 819 nvidia,function = "vi"; 820 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 821 nvidia,tristate = <TEGRA_PIN_DISABLE>; 822 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 823 nvidia,lock = <0>; 824 nvidia,io-reset = <0>; 825 }; 826 827 vi_mclk_pt1 { 828 nvidia,pins = "vi_mclk_pt1"; 829 nvidia,function = "vi"; 830 nvidia,pull = <TEGRA_PIN_PULL_UP>; 831 nvidia,tristate = <TEGRA_PIN_DISABLE>; 832 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 833 }; 834 835 /* HDMI hot-plug-detect */ 836 hdmi_int_pn7 { 837 nvidia,pins = "hdmi_int_pn7"; 838 nvidia,function = "hdmi"; 839 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 840 nvidia,tristate = <TEGRA_PIN_ENABLE>; 841 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 842 }; 843 844 pu4 { 845 nvidia,pins = "pu4"; 846 nvidia,function = "pwm1"; 847 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 848 nvidia,tristate = <TEGRA_PIN_DISABLE>; 849 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 850 }; 851 852 pu5 { 853 nvidia,pins = "pu5"; 854 nvidia,function = "pwm2"; 855 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 856 nvidia,tristate = <TEGRA_PIN_DISABLE>; 857 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 858 }; 859 860 jtag_rtck_pu7 { 861 nvidia,pins = "jtag_rtck_pu7"; 862 nvidia,function = "rtck"; 863 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 864 nvidia,tristate = <TEGRA_PIN_DISABLE>; 865 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 866 }; 867 868 crt_hsync_pv6 { 869 nvidia,pins = "crt_hsync_pv6", 870 "crt_vsync_pv7"; 871 nvidia,function = "crt"; 872 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 873 nvidia,tristate = <TEGRA_PIN_DISABLE>; 874 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 875 }; 876 877 clk1_out_pw4 { 878 nvidia,pins = "clk1_out_pw4"; 879 nvidia,function = "extperiph1"; 880 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 881 nvidia,tristate = <TEGRA_PIN_DISABLE>; 882 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 883 }; 884 885 clk2_out_pw5 { 886 nvidia,pins = "clk2_out_pw5"; 887 nvidia,function = "extperiph2"; 888 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 889 nvidia,tristate = <TEGRA_PIN_DISABLE>; 890 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 891 }; 892 893 clk3_out_pee0 { 894 nvidia,pins = "clk3_out_pee0"; 895 nvidia,function = "extperiph3"; 896 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 897 nvidia,tristate = <TEGRA_PIN_DISABLE>; 898 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 899 }; 900 901 sys_clk_req_pz5 { 902 nvidia,pins = "sys_clk_req_pz5"; 903 nvidia,function = "sysclk"; 904 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 905 nvidia,tristate = <TEGRA_PIN_DISABLE>; 906 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 907 }; 908 909 pbb4 { 910 nvidia,pins = "pbb4"; 911 nvidia,function = "vgp4"; 912 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 913 nvidia,tristate = <TEGRA_PIN_DISABLE>; 914 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 915 }; 916 917 pbb5 { 918 nvidia,pins = "pbb5"; 919 nvidia,function = "vgp5"; 920 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 921 nvidia,tristate = <TEGRA_PIN_DISABLE>; 922 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 923 }; 924 925 pbb6 { 926 nvidia,pins = "pbb6"; 927 nvidia,function = "vgp6"; 928 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 929 nvidia,tristate = <TEGRA_PIN_DISABLE>; 930 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 931 }; 932 933 clk1_req_pee2 { 934 nvidia,pins = "clk1_req_pee2"; 935 nvidia,function = "dap"; 936 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 937 nvidia,tristate = <TEGRA_PIN_DISABLE>; 938 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 939 }; 940 941 clk2_req_pcc5 { 942 nvidia,pins = "clk2_req_pcc5"; 943 nvidia,function = "dap"; 944 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 945 nvidia,tristate = <TEGRA_PIN_DISABLE>; 946 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 947 }; 948 949 clk3_req_pee1 { 950 nvidia,pins = "clk3_req_pee1"; 951 nvidia,function = "dev3"; 952 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 953 nvidia,tristate = <TEGRA_PIN_DISABLE>; 954 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 955 }; 956 957 owr { 958 nvidia,pins = "owr"; 959 nvidia,function = "owr"; 960 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 961 nvidia,tristate = <TEGRA_PIN_DISABLE>; 962 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 963 }; 964 965 pv2 { 966 nvidia,pins = "pv2", 967 "kb_row5_pr5"; 968 nvidia,function = "owr"; 969 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 970 nvidia,tristate = <TEGRA_PIN_DISABLE>; 971 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 972 }; 973 974 pbb3 { 975 nvidia,pins = "pbb3"; 976 nvidia,function = "vgp3"; 977 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 978 nvidia,tristate = <TEGRA_PIN_DISABLE>; 979 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 980 }; 981 982 pbb7 { 983 nvidia,pins = "pbb7"; 984 nvidia,function = "i2s4"; 985 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 986 nvidia,tristate = <TEGRA_PIN_DISABLE>; 987 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 988 }; 989 990 cam_mclk_pcc0 { 991 nvidia,pins = "cam_mclk_pcc0"; 992 nvidia,function = "vi_alt3"; 993 nvidia,pull = <TEGRA_PIN_PULL_UP>; 994 nvidia,tristate = <TEGRA_PIN_DISABLE>; 995 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 996 }; 997 998 /* GPIO power/drive control */ 999 drive_dap1 { 1000 nvidia,pins = "drive_dap1", 1001 "drive_dap2", 1002 "drive_dbg", 1003 "drive_at5", 1004 "drive_gme", 1005 "drive_ddc", 1006 "drive_ao1", 1007 "drive_uart3"; 1008 nvidia,high-speed-mode = <0>; 1009 nvidia,schmitt = <TEGRA_PIN_ENABLE>; 1010 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 1011 nvidia,pull-down-strength = <31>; 1012 nvidia,pull-up-strength = <31>; 1013 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 1014 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 1015 }; 1016 1017 drive_sdio1 { 1018 nvidia,pins = "drive_sdio1"; 1019 nvidia,high-speed-mode = <0>; 1020 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 1021 nvidia,pull-down-strength = <5>; 1022 nvidia,pull-up-strength = <5>; 1023 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; 1024 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; 1025 }; 1026 1027 drive_sdio3 { 1028 nvidia,pins = "drive_sdio3"; 1029 nvidia,high-speed-mode = <0>; 1030 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 1031 nvidia,pull-down-strength = <46>; 1032 nvidia,pull-up-strength = <42>; 1033 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; 1034 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; 1035 }; 1036 1037 drive_gma { 1038 nvidia,pins = "drive_gma", 1039 "drive_gmb", 1040 "drive_gmc", 1041 "drive_gmd"; 1042 nvidia,pull-down-strength = <9>; 1043 nvidia,pull-up-strength = <9>; 1044 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 1045 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 1046 }; 1047 1048 drive_lcd2 { 1049 nvidia,pins = "drive_lcd2"; 1050 nvidia,high-speed-mode = <0>; 1051 nvidia,schmitt = <TEGRA_PIN_ENABLE>; 1052 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>; 1053 nvidia,pull-down-strength = <20>; 1054 nvidia,pull-up-strength = <20>; 1055 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 1056 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 1057 }; 1058 }; 1059 }; 1060 1061 uarta: serial@70006000 { 1062 status = "okay"; 1063 }; 1064 1065 pwm: pwm@7000a000 { 1066 status = "okay"; 1067 }; 1068 1069 pwr_i2c: i2c@7000d000 { 1070 status = "okay"; 1071 clock-frequency = <400000>; 1072 1073 /* Texas Instruments TPS659110 PMIC */ 1074 pmic: tps65911@2d { 1075 compatible = "ti,tps65911"; 1076 reg = <0x2d>; 1077 1078 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1079 #interrupt-cells = <2>; 1080 interrupt-controller; 1081 1082 ti,system-power-controller; 1083 1084 #gpio-cells = <2>; 1085 gpio-controller; 1086 1087 regulators { 1088 vdd_1v8_vio: vddio { 1089 regulator-name = "vdd_1v8_gen"; 1090 regulator-min-microvolt = <1800000>; 1091 regulator-max-microvolt = <1800000>; 1092 regulator-always-on; 1093 regulator-boot-on; 1094 }; 1095 1096 /* eMMC VDD */ 1097 vcore_emmc: ldo1 { 1098 regulator-name = "vdd_emmc_core"; 1099 regulator-min-microvolt = <3300000>; 1100 regulator-max-microvolt = <3300000>; 1101 regulator-boot-on; 1102 }; 1103 1104 /* uSD slot VDD */ 1105 vdd_usd: ldo2 { 1106 regulator-name = "vdd_usd"; 1107 regulator-min-microvolt = <3100000>; 1108 regulator-max-microvolt = <3100000>; 1109 regulator-boot-on; 1110 }; 1111 1112 /* uSD slot VDDIO */ 1113 vddio_usd: ldo3 { 1114 regulator-name = "vddio_usd"; 1115 regulator-min-microvolt = <3100000>; 1116 regulator-max-microvolt = <3100000>; 1117 regulator-always-on; 1118 regulator-boot-on; 1119 }; 1120 }; 1121 }; 1122 }; 1123 1124 sdmmc1: sdhci@78000000 { 1125 status = "okay"; 1126 bus-width = <4>; 1127 1128 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 1129 1130 vmmc-supply = <&vdd_usd>; 1131 vqmmc-supply = <&vddio_usd>; 1132 }; 1133 1134 sdmmc4: sdhci@78000600 { 1135 status = "okay"; 1136 bus-width = <8>; 1137 non-removable; 1138 1139 vmmc-supply = <&vcore_emmc>; 1140 vqmmc-supply = <&vdd_1v8_vio>; 1141 }; 1142 1143 usb1: usb@7d000000 { 1144 status = "okay"; 1145 dr_mode = "otg"; 1146 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_HIGH>; 1147 }; 1148 1149 usb-phy@7d000000 { 1150 status = "okay"; 1151 nvidia,hssync-start-delay = <0>; 1152 nvidia,xcvr-lsfslew = <2>; 1153 nvidia,xcvr-lsrslew = <2>; 1154 }; 1155 1156 usb3: usb@7d008000 { 1157 status = "okay"; 1158 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>; 1159 }; 1160 1161 usb-phy@7d008000 { 1162 status = "okay"; 1163 }; 1164 1165 backlight: backlight { 1166 compatible = "pwm-backlight"; 1167 1168 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; 1169 power-supply = <&vdd_5v0_bl>; 1170 pwms = <&pwm 0 5000000>; 1171 1172 brightness-levels = <1 35 70 105 140 175 210 255>; 1173 default-brightness-level = <5>; 1174 }; 1175 1176 /* PMIC has a built-in 32KHz oscillator which is used by PMC */ 1177 clk32k_in: clock-32k { 1178 compatible = "fixed-clock"; 1179 #clock-cells = <0>; 1180 clock-frequency = <32768>; 1181 clock-output-names = "pmic-oscillator"; 1182 }; 1183 1184 gpio-keys { 1185 compatible = "gpio-keys"; 1186 1187 key-power { 1188 label = "Power"; 1189 gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; 1190 linux,code = <KEY_ENTER>; 1191 }; 1192 1193 key-volume-up { 1194 label = "Volume Up"; 1195 gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; 1196 linux,code = <KEY_UP>; 1197 }; 1198 1199 key-volume-down { 1200 label = "Volume Down"; 1201 gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>; 1202 linux,code = <KEY_DOWN>; 1203 }; 1204 }; 1205 1206 display-panel { 1207 compatible = "hannstar,hsd101pww2", "simple-panel"; 1208 1209 power-supply = <&vdd_pnl_reg>; 1210 backlight = <&backlight>; 1211 1212 display-timings { 1213 timing@0 { 1214 /* 1280x800@60Hz */ 1215 clock-frequency = <68000000>; 1216 1217 hactive = <1280>; 1218 hfront-porch = <48>; 1219 hback-porch = <18>; 1220 hsync-len = <30>; 1221 1222 vactive = <800>; 1223 vfront-porch = <3>; 1224 vback-porch = <12>; 1225 vsync-len = <5>; 1226 }; 1227 }; 1228 1229 port { 1230 panel_input: endpoint { 1231 remote-endpoint = <&bridge_output>; 1232 }; 1233 }; 1234 }; 1235 1236 /* Texas Instruments SN75LVDS83B LVDS Transmitter */ 1237 lvds-encoder { 1238 compatible = "ti,sn75lvds83", "lvds-encoder"; 1239 1240 powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; 1241 power-supply = <&vdd_3v3_sys>; 1242 1243 ports { 1244 #address-cells = <1>; 1245 #size-cells = <0>; 1246 1247 port@0 { 1248 reg = <0>; 1249 1250 bridge_input: endpoint { 1251 remote-endpoint = <&dpi_output>; 1252 }; 1253 }; 1254 1255 port@1 { 1256 reg = <1>; 1257 1258 bridge_output: endpoint { 1259 remote-endpoint = <&panel_input>; 1260 }; 1261 }; 1262 }; 1263 }; 1264 1265 vdd_3v3_sys: regulator-3v { 1266 compatible = "regulator-fixed"; 1267 regulator-name = "vdd_3v3_sys"; 1268 regulator-min-microvolt = <3300000>; 1269 regulator-max-microvolt = <3300000>; 1270 regulator-always-on; 1271 regulator-boot-on; 1272 }; 1273 1274 vdd_pnl_reg: regulator-pnl { 1275 compatible = "regulator-fixed"; 1276 regulator-name = "vdd_panel"; 1277 regulator-min-microvolt = <3300000>; 1278 regulator-max-microvolt = <3300000>; 1279 gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; 1280 enable-active-high; 1281 }; 1282 1283 vdd_5v0_bl: regulator-bl { 1284 compatible = "regulator-fixed"; 1285 regulator-name = "vdd_5v0_bl"; 1286 regulator-min-microvolt = <5000000>; 1287 regulator-max-microvolt = <5000000>; 1288 gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; 1289 enable-active-high; 1290 }; 1291}; 1292