1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef __ASM_ACPI_TABLE_H__ 4 #define __ASM_ACPI_TABLE_H__ 5 6 #ifndef __ACPI__ 7 #ifndef __ASSEMBLY__ 8 9 #include <acpi/acpi_table.h> 10 11 /** 12 * acpi_write_madt_gicc() - Write out a MADT GICC sub-table 13 * 14 * Write out the GIC CPU Interface sub-table. 15 * 16 * @gicc: Pointer to place to put the sub-table 17 * @cpu_num: GIC's CPU Interface Number 18 * @perf_gsiv: The GSIV used for Performance Monitoring Interrupts 19 * @phys_base: Address at which the processor can access this 20 * GIC CPU Interface 21 * @gicv: Address of the GIC virtual CPU interface registers 22 * @gich: Address of the GIC virtual interface control block 23 * registers 24 * @vgic_maint_irq: GSIV for Virtual GIC maintenance interrupt 25 * @gicr_base: Physical address of the associated Redistributor 26 * @mpidr: MPIDR as defined by ARM architecture 27 * @efficiency: Describes the relative power efficiency 28 */ 29 void acpi_write_madt_gicc(struct acpi_madt_gicc *gicc, uint cpu_num, 30 uint perf_gsiv, ulong phys_base, ulong gicv, 31 ulong gich, uint vgic_maint_irq, u64 gicr_base, 32 ulong mpidr, uint efficiency); 33 34 /** 35 * acpi_write_madt_gicd() - Write out a MADT GICD sub-table 36 * 37 * Write out the GIC Distributor sub-table. 38 * 39 * @gicd: Pointer to place to put the sub-table 40 * @gic_id: This GIC Distributor's hardware ID 41 * @phys_base: The 64-bit physical address for this Distributor 42 * @gic_version: GIC version 43 */ 44 void acpi_write_madt_gicd(struct acpi_madt_gicd *gicd, uint gic_id, 45 ulong phys_base, uint gic_version); 46 47 /** 48 * acpi_write_madt_gicr() - Write out a MADT GICR sub-table 49 * 50 * Write out the GIC Redistributor sub-table. 51 * 52 * @gicr: Pointer to place to put the sub-table 53 * @discovery_range_base_address: Physical address of a page range 54 * containing all GIC Redistributors 55 * @discovery_range_length: Length of the GIC Redistributor 56 * Discovery page range 57 */ 58 void acpi_write_madt_gicr(struct acpi_madt_gicr *gicr, 59 u64 discovery_range_base_address, 60 u32 discovery_range_length); 61 62 /** 63 * acpi_write_madt_its() - Write out a MADT ITS sub-table 64 * 65 * Write out the GIC Interrupt Translation Service sub-table. 66 * 67 * @its: Pointer to place to put the sub-table 68 * @its_id: Uniqueue GIC ITS ID 69 * @physical_base_address: Physical address for the Interrupt 70 * Translation Service 71 */ 72 void acpi_write_madt_its(struct acpi_madt_its *its, 73 u32 its_id, 74 u64 physical_base_address); 75 76 /** 77 * acpi_pptt_add_proc() - Write out a PPTT processor sub-table 78 * 79 * Write out the Processor Properties Topology Table processor sub-table. 80 * 81 * @ctx: ACPI context pointer 82 * @flags: Processor Structure Flags 83 * @parent: Reference to parent processor 84 * @proc_id: ACPI processor ID as defined in MADT 85 * @num_resources: Number of resource structure references 86 * @resource_list: References to other PPTT structures 87 * Return: offset from start of PPTT in bytes 88 */ 89 int acpi_pptt_add_proc(struct acpi_ctx *ctx, const u32 flags, const u32 parent, 90 const u32 proc_id, const u32 num_resources, 91 const u32 *resource_list); 92 93 /** 94 * acpi_pptt_add_cache() - Write out a PPTT cache sub-table 95 * 96 * Write out the Processor Properties Topology Table cache sub-table. 97 * 98 * @ctx: ACPI context pointer 99 * @flags: Cache Structure Flags 100 * @next_cache_level: Reference to next level of cache 101 * @size: Size of the cache in bytes 102 * @sets: Number of sets in the cache 103 * @assoc: Integer number of ways 104 * @attributes: Allocation type, Cache type, policy 105 * @line_size: Line size in bytes 106 * Return: offset from start of PPTT in bytes 107 */ 108 int acpi_pptt_add_cache(struct acpi_ctx *ctx, const u32 flags, 109 const u32 next_cache_level, const u32 size, 110 const u32 sets, const u8 assoc, const u8 attributes, 111 const u16 line_size); 112 113 /* Multi-processor Startup for ARM Platforms */ 114 /** 115 * struct acpi_pp_page - MP startup handshake mailbox 116 * 117 * Defines a 4096 byte memory region that is used for starting secondary CPUs on 118 * an Arm system that follows the "Multi-processor Startup for ARM Platforms" spec. 119 * 120 * @cpu_id: MPIDR as returned by the Multiprocessor Affinity Register. 121 * On 32bit Arm systems the upper bits are unused. 122 * @jumping_address: On 32bit Arm systems the address must be below 4 GiB 123 * @os_reserved: Reserved for OS use. Firmware must not access this memory. 124 * @spinning_code: Reserved for firmware use. OS must not access this memory. 125 * The spinning code will be installed by firmware and the secondary 126 * CPUs will enter it before the control is handed over to the OS. 127 */ 128 struct acpi_pp_page { 129 u64 cpu_id; 130 u64 jumping_address; 131 u8 os_reserved[2032]; 132 u8 spinning_code[2048]; 133 } __packed; 134 135 #endif /* !__ASSEMBLY__ */ 136 #endif /* !__ACPI__ */ 137 138 /* Multi-processor Startup for ARM Platforms defines */ 139 #define ACPI_PP_CPU_ID_INVALID 0xffffffff 140 #define ACPI_PP_JMP_ADR_INVALID 0 141 #define ACPI_PP_PAGE_SIZE 4096 142 #define ACPI_PP_CPU_ID_OFFSET 0 143 #define ACPI_PP_CPU_JMP_OFFSET 8 144 #define ACPI_PP_CPU_CODE_OFFSET 2048 145 #define ACPI_PP_VERSION 1 146 147 #endif /* __ASM_ACPI_TABLE_H__ */ 148