1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2021 NXP 4 */ 5 6 #ifndef _ASM_ARCH_IMX8ULP_CLOCK_H 7 #define _ASM_ARCH_IMX8ULP_CLOCK_H 8 9 #include <asm/arch/pcc.h> 10 #include <asm/arch/cgc.h> 11 12 #define MHZ(X) ((X) * 1000000UL) 13 14 /* Mainly for compatible to imx common code. */ 15 enum mxc_clock { 16 MXC_ARM_CLK = 0, 17 MXC_AHB_CLK, 18 MXC_IPG_CLK, 19 MXC_UART_CLK, 20 MXC_CSPI_CLK, 21 MXC_AXI_CLK, 22 MXC_DDR_CLK, 23 MXC_ESDHC_CLK, 24 MXC_ESDHC2_CLK, 25 MXC_ESDHC3_CLK, 26 MXC_I2C_CLK, 27 }; 28 29 u32 mxc_get_clock(enum mxc_clock clk); 30 u32 get_lpuart_clk(void); 31 #ifdef CONFIG_SYS_I2C_IMX_LPI2C 32 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); 33 u32 imx_get_i2cclk(unsigned int i2c_num); 34 #endif 35 void enable_usboh3_clk(unsigned char enable); 36 int enable_usb_pll(ulong usb_phy_base); 37 #ifdef CONFIG_MXC_OCOTP 38 void enable_ocotp_clk(unsigned char enable); 39 #endif 40 void init_clk_usdhc(u32 index); 41 void init_clk_fspi(int index); 42 void init_clk_ddr(void); 43 int set_ddr_clk(u32 phy_freq_mhz); 44 void clock_init_early(void); 45 void clock_init_late(void); 46 void cgc1_enet_stamp_sel(u32 clk_src); 47 void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz); 48 void reset_lcdclk(void); 49 void enable_mipi_dsi_clk(unsigned char enable); 50 void enable_adc1_clk(bool enable); 51 #endif 52