1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuration settings for the Allwinner A64 (sun50i) CPU 4 */ 5 6 #include <asm/arch/cpu.h> 7 8 #if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_XPL_BUILD) 9 /* reserve space for BOOT0 header information */ 10 b reset 11 .space 1532 12 #elif defined(CONFIG_ARM_BOOT_HOOK_RMR) 13 /* 14 * Switch into AArch64 if needed. 15 * Refer to arch/arm/mach-sunxi/rmr_switch.S for the original source. 16 */ 17 tst x0, x0 // this is "b #0x84" in ARM 18 b reset 19 .space 0x78 20 .word fel_stash - . 21 22 .word 0xe24f000c // sub r0, pc, #12 // @(fel_stash - .) 23 .word 0xe51f1010 // ldr r1, [pc, #-16] // fel_stash - . 24 .word 0xe0800001 // add r0, r0, r1 25 .word 0xe580d000 // str sp, [r0] 26 .word 0xe580e004 // str lr, [r0, #4] 27 .word 0xe10fe000 // mrs lr, CPSR 28 .word 0xe580e008 // str lr, [r0, #8] 29 .word 0xe101e300 // mrs lr, SP_irq 30 .word 0xe580e014 // str lr, [r0, #20] 31 .word 0xee11ef10 // mrc 15, 0, lr, cr1, cr0, {0} 32 .word 0xe580e00c // str lr, [r0, #12] 33 .word 0xee1cef10 // mrc 15, 0, lr, cr12, cr0, {0} 34 .word 0xe580e010 // str lr, [r0, #16] 35 #ifdef CONFIG_MACH_SUN55I_A523 36 .word 0xee1cefbc // mrc 15, 0, lr, cr12, cr12, {5} 37 .word 0xe31e0001 // tst lr, #1 38 .word 0x0a000003 // beq cc <start32+0x48> 39 .word 0xee14ef16 // mrc 15, 0, lr, cr4, cr6, {0} 40 .word 0xe580e018 // str lr, [r0, #24] 41 .word 0xee1ceffc // mrc 15, 0, lr, cr12, cr12, {7} 42 .word 0xe580e01c // str lr, [r0, #28] 43 #endif 44 .word 0xe59f1034 // ldr r1, [pc, #52] ; RVBAR_ADDRESS 45 .word 0xe59f0034 // ldr r0, [pc, #52] ; SUNXI_SRAMC_BASE 46 .word 0xe5900024 // ldr r0, [r0, #36] ; SRAM_VER_REG 47 .word 0xe21000ff // ands r0, r0, #255 ; 0xff 48 .word 0x159f102c // ldrne r1, [pc, #44] ; RVBAR_ALTERNATIVE 49 .word 0xe59f002c // ldr r0, [pc, #44] ; CONFIG_*TEXT_BASE 50 .word 0xe5810000 // str r0, [r1] 51 .word 0xf57ff04f // dsb sy 52 .word 0xf57ff06f // isb sy 53 .word 0xee1c0f50 // mrc 15, 0, r0, cr12, cr0, {2} ; RMR 54 .word 0xe3800003 // orr r0, r0, #3 55 .word 0xee0c0f50 // mcr 15, 0, r0, cr12, cr0, {2} ; RMR 56 .word 0xf57ff06f // isb sy 57 .word 0xe320f003 // wfi 58 .word 0xeafffffd // b @wfi 59 60 .word CONFIG_SUNXI_RVBAR_ADDRESS // writable RVBAR mapping addr 61 .word SUNXI_SRAMC_BASE 62 .word CONFIG_SUNXI_RVBAR_ALTERNATIVE // address for die variant 63 #ifdef CONFIG_XPL_BUILD 64 .word CONFIG_SPL_TEXT_BASE 65 #else 66 .word CONFIG_TEXT_BASE 67 #endif 68 #else 69 /* normal execution */ 70 b reset 71 #endif 72