1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  *  (C) Copyright 2010,2011
4  *  NVIDIA Corporation <www.nvidia.com>
5  */
6 
7 #ifndef _FUSE_H_
8 #define _FUSE_H_
9 
10 /* FUSE registers */
11 struct fuse_regs {
12 	u32 reserved0[64];		/* 0x00 - 0xFC: */
13 	u32 production_mode;		/* 0x100: FUSE_PRODUCTION_MODE */
14 	u32 reserved1[3];		/* 0x104 - 0x10c: */
15 	u32 sku_info;			/* 0x110 */
16 	u32 reserved2[13];		/* 0x114 - 0x144: */
17 	u32 fa;				/* 0x148: FUSE_FA */
18 	u32 reserved3[21];		/* 0x14C - 0x19C: */
19 	u32 security_mode;		/* 0x1A0: FUSE_SECURITY_MODE */
20 	u32 sbk[4];			/* 0x1A4 - 0x1B4 */
21 };
22 
23 /* Defines the supported operating modes */
24 enum fuse_operating_mode {
25 	MODE_UNDEFINED = 0,
26 	MODE_PRODUCTION = 3,
27 	MODE_ODM_PRODUCTION_SECURE = 4,
28 	MODE_ODM_PRODUCTION_OPEN = 5,
29 };
30 
31 /**
32  * Initializes fuse hardware
33  */
34 void tegra_fuse_init(void);
35 
36 /**
37  * Calculate SoC UID
38  *
39  * Return: uid if ok, 0 on error
40  */
41 unsigned long long tegra_chip_uid(void);
42 
43 /**
44  * Gives the current operating mode from fuses
45  *
46  * @return current operating mode
47  */
48 enum fuse_operating_mode tegra_fuse_get_operation_mode(void);
49 
50 #endif	/* ifndef _FUSE_H_ */
51