1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2010, 2011 4 * NVIDIA Corporation <www.nvidia.com> 5 */ 6 7 #ifndef _WARM_BOOT_H_ 8 #define _WARM_BOOT_H_ 9 10 #define STRAP_OPT_A_RAM_CODE_SHIFT 4 11 #define STRAP_OPT_A_RAM_CODE_MASK (0xf << STRAP_OPT_A_RAM_CODE_SHIFT) 12 13 /* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) */ 14 enum { 15 HASH_LENGTH = 4 16 }; 17 18 /* Defines the storage for a hash value (128 bits) */ 19 struct hash { 20 u32 hash[HASH_LENGTH]; 21 }; 22 23 /* 24 * Defines the code header information for the boot rom. 25 * 26 * The code immediately follows the code header. 27 * 28 * Note that the code header needs to be 16 bytes aligned to preserve 29 * the alignment of relevant data for hash and decryption computations without 30 * requiring extra copies to temporary memory areas. 31 */ 32 struct wb_header { 33 u32 length_insecure; /* length of the code header */ 34 u32 reserved[3]; 35 struct hash hash; /* hash of header+code, starts next field*/ 36 struct hash random_aes_block; /* a data block to aid security. */ 37 u32 length_secure; /* length of the code header */ 38 u32 destination; /* destination address to put the wb code */ 39 u32 entry_point; /* execution address of the wb code */ 40 u32 code_length; /* length of the code */ 41 }; 42 43 /* 44 * The warm boot code needs direct access to these registers since it runs in 45 * SRAM and cannot call other U-Boot code. 46 */ 47 union osc_ctrl_reg { 48 struct { 49 u32 xoe:1; 50 u32 xobp:1; 51 u32 reserved0:2; 52 u32 xofs:6; 53 u32 reserved1:2; 54 u32 xods:5; 55 u32 reserved2:3; 56 u32 oscfi_spare:8; 57 u32 pll_ref_div:2; 58 u32 osc_freq:2; 59 }; 60 u32 word; 61 }; 62 63 union pllx_base_reg { 64 struct { 65 u32 divm:5; 66 u32 reserved0:3; 67 u32 divn:10; 68 u32 reserved1:2; 69 u32 divp:3; 70 u32 reserved2:4; 71 u32 lock:1; 72 u32 reserved3:1; 73 u32 ref_dis:1; 74 u32 enable:1; 75 u32 bypass:1; 76 }; 77 u32 word; 78 }; 79 80 union pllx_misc_reg { 81 struct { 82 u32 vcocon:4; 83 u32 lfcon:4; 84 u32 cpcon:4; 85 u32 lock_sel:6; 86 u32 reserved0:1; 87 u32 lock_enable:1; 88 u32 reserved1:1; 89 u32 dccon:1; 90 u32 pts:2; 91 u32 reserved2:6; 92 u32 out1_div_byp:1; 93 u32 out1_inv_clk:1; 94 }; 95 u32 word; 96 }; 97 98 /* 99 * TODO: This register is not documented in the TRM yet. We could move this 100 * into the EMC and give it a proper interface, but not while it is 101 * undocumented. 102 */ 103 union scratch3_reg { 104 struct { 105 u32 pllx_base_divm:5; 106 u32 pllx_base_divn:10; 107 u32 pllx_base_divp:3; 108 u32 pllx_misc_lfcon:4; 109 u32 pllx_misc_cpcon:4; 110 }; 111 u32 word; 112 }; 113 114 /** 115 * Save warmboot memory settings for a later resume 116 * 117 * Return: 0 if ok, -1 on error 118 */ 119 int warmboot_save_sdram_params(void); 120 121 int warmboot_prepare_code(u32 seg_address, u32 seg_length); 122 void wb_start(void); /* Start of WB assembly code */ 123 void wb_end(void); /* End of WB assembly code */ 124 125 #endif 126