1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2018 NXP 4 */ 5 6 #define MIDR_PARTNUM_CORTEX_A35 0xD04 7 #define MIDR_PARTNUM_CORTEX_A53 0xD03 8 #define MIDR_PARTNUM_CORTEX_A55 0xD05 9 #define MIDR_PARTNUM_CORTEX_A57 0xD07 10 #define MIDR_PARTNUM_CORTEX_A72 0xD08 11 #define MIDR_PARTNUM_CORTEX_A73 0xD09 12 #define MIDR_PARTNUM_CORTEX_A75 0xD0A 13 #define MIDR_PARTNUM_CORTEX_A76 0xD0B 14 #define MIDR_PARTNUM_SHIFT 0x4 15 #define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT) 16 read_midr(void)17static inline unsigned int read_midr(void) 18 { 19 unsigned long val; 20 21 asm volatile("mrs %0, midr_el1" : "=r" (val)); 22 23 return val; 24 } 25 26 #define is_cortex_a(__n) \ 27 static inline int is_cortex_a##__n(void) \ 28 { \ 29 unsigned int midr = read_midr(); \ 30 midr &= MIDR_PARTNUM_MASK; \ 31 midr >>= MIDR_PARTNUM_SHIFT; \ 32 return midr == MIDR_PARTNUM_CORTEX_A##__n; \ 33 } 34 35 is_cortex_a(35) 36 is_cortex_a(53) 37 is_cortex_a(55) 38 is_cortex_a(57) 39 is_cortex_a(72) 40 is_cortex_a(73) 41 is_cortex_a(75) 42 is_cortex_a(76) 43