1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #ifndef __ASM_ESR_H
8 #define __ASM_ESR_H
9
10 #include <stdbool.h>
11 #include <asm/memory.h>
12 #include <linux/const.h>
13
14 #define ESR_ELx_EC_UNKNOWN (0x00)
15 #define ESR_ELx_EC_WFx (0x01)
16 /* Unallocated EC: 0x02 */
17 #define ESR_ELx_EC_CP15_32 (0x03)
18 #define ESR_ELx_EC_CP15_64 (0x04)
19 #define ESR_ELx_EC_CP14_MR (0x05)
20 #define ESR_ELx_EC_CP14_LS (0x06)
21 #define ESR_ELx_EC_FP_ASIMD (0x07)
22 #define ESR_ELx_EC_CP10_ID (0x08) /* EL2 only */
23 #define ESR_ELx_EC_PAC (0x09) /* EL2 and above */
24 /* Unallocated EC: 0x0A - 0x0B */
25 #define ESR_ELx_EC_CP14_64 (0x0C)
26 #define ESR_ELx_EC_BTI (0x0D)
27 #define ESR_ELx_EC_ILL (0x0E)
28 /* Unallocated EC: 0x0F - 0x10 */
29 #define ESR_ELx_EC_SVC32 (0x11)
30 #define ESR_ELx_EC_HVC32 (0x12) /* EL2 only */
31 #define ESR_ELx_EC_SMC32 (0x13) /* EL2 and above */
32 /* Unallocated EC: 0x14 */
33 #define ESR_ELx_EC_SVC64 (0x15)
34 #define ESR_ELx_EC_HVC64 (0x16) /* EL2 and above */
35 #define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */
36 #define ESR_ELx_EC_SYS64 (0x18)
37 #define ESR_ELx_EC_SVE (0x19)
38 #define ESR_ELx_EC_ERET (0x1a) /* EL2 only */
39 /* Unallocated EC: 0x1B */
40 #define ESR_ELx_EC_FPAC (0x1C) /* EL1 and above */
41 /* Unallocated EC: 0x1D - 0x1E */
42 #define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */
43 #define ESR_ELx_EC_IABT_LOW (0x20)
44 #define ESR_ELx_EC_IABT_CUR (0x21)
45 #define ESR_ELx_EC_PC_ALIGN (0x22)
46 /* Unallocated EC: 0x23 */
47 #define ESR_ELx_EC_DABT_LOW (0x24)
48 #define ESR_ELx_EC_DABT_CUR (0x25)
49 #define ESR_ELx_EC_SP_ALIGN (0x26)
50 /* Unallocated EC: 0x27 */
51 #define ESR_ELx_EC_FP_EXC32 (0x28)
52 /* Unallocated EC: 0x29 - 0x2B */
53 #define ESR_ELx_EC_FP_EXC64 (0x2C)
54 /* Unallocated EC: 0x2D - 0x2E */
55 #define ESR_ELx_EC_SERROR (0x2F)
56 #define ESR_ELx_EC_BREAKPT_LOW (0x30)
57 #define ESR_ELx_EC_BREAKPT_CUR (0x31)
58 #define ESR_ELx_EC_SOFTSTP_LOW (0x32)
59 #define ESR_ELx_EC_SOFTSTP_CUR (0x33)
60 #define ESR_ELx_EC_WATCHPT_LOW (0x34)
61 #define ESR_ELx_EC_WATCHPT_CUR (0x35)
62 /* Unallocated EC: 0x36 - 0x37 */
63 #define ESR_ELx_EC_BKPT32 (0x38)
64 /* Unallocated EC: 0x39 */
65 #define ESR_ELx_EC_VECTOR32 (0x3A) /* EL2 only */
66 /* Unallocated EC: 0x3B */
67 #define ESR_ELx_EC_BRK64 (0x3C)
68 /* Unallocated EC: 0x3D - 0x3F */
69 #define ESR_ELx_EC_MAX (0x3F)
70
71 #define ESR_ELx_EC_SHIFT (26)
72 #define ESR_ELx_EC_WIDTH (6)
73 #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
74 #define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
75
76 #define ESR_ELx_IL_SHIFT (25)
77 #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
78 #define ESR_ELx_ISS_MASK (ESR_ELx_IL - 1)
79
80 /* ISS field definitions shared by different classes */
81 #define ESR_ELx_WNR_SHIFT (6)
82 #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
83
84 /* Asynchronous Error Type */
85 #define ESR_ELx_IDS_SHIFT (24)
86 #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
87 #define ESR_ELx_AET_SHIFT (10)
88 #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
89
90 #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
91 #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
92 #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
93 #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
94 #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
95
96 /* Shared ISS field definitions for Data/Instruction aborts */
97 #define ESR_ELx_SET_SHIFT (11)
98 #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT)
99 #define ESR_ELx_FnV_SHIFT (10)
100 #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT)
101 #define ESR_ELx_EA_SHIFT (9)
102 #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT)
103 #define ESR_ELx_S1PTW_SHIFT (7)
104 #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT)
105
106 /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
107 #define ESR_ELx_FSC (0x3F)
108 #define ESR_ELx_FSC_TYPE (0x3C)
109 #define ESR_ELx_FSC_LEVEL (0x03)
110 #define ESR_ELx_FSC_EXTABT (0x10)
111 #define ESR_ELx_FSC_MTE (0x11)
112 #define ESR_ELx_FSC_SERROR (0x11)
113 #define ESR_ELx_FSC_ACCESS (0x08)
114 #define ESR_ELx_FSC_FAULT (0x04)
115 #define ESR_ELx_FSC_PERM (0x0C)
116
117 /* ISS field definitions for Data Aborts */
118 #define ESR_ELx_ISV_SHIFT (24)
119 #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
120 #define ESR_ELx_SAS_SHIFT (22)
121 #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
122 #define ESR_ELx_SSE_SHIFT (21)
123 #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT)
124 #define ESR_ELx_SRT_SHIFT (16)
125 #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
126 #define ESR_ELx_SF_SHIFT (15)
127 #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT)
128 #define ESR_ELx_AR_SHIFT (14)
129 #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT)
130 #define ESR_ELx_CM_SHIFT (8)
131 #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT)
132
133 /* ISS field definitions for exceptions taken in to Hyp */
134 #define ESR_ELx_CV (UL(1) << 24)
135 #define ESR_ELx_COND_SHIFT (20)
136 #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
137 #define ESR_ELx_WFx_ISS_TI (UL(1) << 0)
138 #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
139 #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
140 #define ESR_ELx_xVC_IMM_MASK ((1UL << 16) - 1)
141
142 #define DISR_EL1_IDS (UL(1) << 24)
143 /*
144 * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
145 * different things in the future...
146 */
147 #define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)
148
149 /* ESR value templates for specific events */
150 #define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI)
151 #define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \
152 ESR_ELx_WFx_ISS_WFI)
153
154 /* BRK instruction trap from AArch64 state */
155 #define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff
156
157 /* ISS field definitions for System instruction traps */
158 #define ESR_ELx_SYS64_ISS_RES0_SHIFT 22
159 #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
160 #define ESR_ELx_SYS64_ISS_DIR_MASK 0x1
161 #define ESR_ELx_SYS64_ISS_DIR_READ 0x1
162 #define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0
163
164 #define ESR_ELx_SYS64_ISS_RT_SHIFT 5
165 #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
166 #define ESR_ELx_SYS64_ISS_CRM_SHIFT 1
167 #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
168 #define ESR_ELx_SYS64_ISS_CRN_SHIFT 10
169 #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
170 #define ESR_ELx_SYS64_ISS_OP1_SHIFT 14
171 #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
172 #define ESR_ELx_SYS64_ISS_OP2_SHIFT 17
173 #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
174 #define ESR_ELx_SYS64_ISS_OP0_SHIFT 20
175 #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
176 #define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
177 ESR_ELx_SYS64_ISS_OP1_MASK | \
178 ESR_ELx_SYS64_ISS_OP2_MASK | \
179 ESR_ELx_SYS64_ISS_CRN_MASK | \
180 ESR_ELx_SYS64_ISS_CRM_MASK)
181 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
182 (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
183 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
184 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
185 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
186 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
187
188 #define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \
189 ESR_ELx_SYS64_ISS_DIR_MASK)
190 #define ESR_ELx_SYS64_ISS_RT(esr) \
191 (((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
192 /*
193 * User space cache operations have the following sysreg encoding
194 * in System instructions.
195 * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
196 */
197 #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14
198 #define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13
199 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12
200 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11
201 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10
202 #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5
203
204 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
205 ESR_ELx_SYS64_ISS_OP1_MASK | \
206 ESR_ELx_SYS64_ISS_OP2_MASK | \
207 ESR_ELx_SYS64_ISS_CRN_MASK | \
208 ESR_ELx_SYS64_ISS_DIR_MASK)
209 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
210 (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
211 ESR_ELx_SYS64_ISS_DIR_WRITE)
212 /*
213 * User space MRS operations which are supported for emulation
214 * have the following sysreg encoding in System instructions.
215 * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
216 */
217 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
218 ESR_ELx_SYS64_ISS_OP1_MASK | \
219 ESR_ELx_SYS64_ISS_CRN_MASK | \
220 ESR_ELx_SYS64_ISS_DIR_MASK)
221 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
222 (ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \
223 ESR_ELx_SYS64_ISS_DIR_READ)
224
225 #define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
226 #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \
227 ESR_ELx_SYS64_ISS_DIR_READ)
228
229 #define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
230 ESR_ELx_SYS64_ISS_DIR_READ)
231
232 #define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \
233 ESR_ELx_SYS64_ISS_DIR_READ)
234
235 #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
236 ESR_ELx_SYS64_ISS_DIR_READ)
237
238 #define esr_sys64_to_sysreg(e) \
239 sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \
240 ESR_ELx_SYS64_ISS_OP0_SHIFT), \
241 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
242 ESR_ELx_SYS64_ISS_OP1_SHIFT), \
243 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
244 ESR_ELx_SYS64_ISS_CRN_SHIFT), \
245 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
246 ESR_ELx_SYS64_ISS_CRM_SHIFT), \
247 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
248 ESR_ELx_SYS64_ISS_OP2_SHIFT))
249
250 #define esr_cp15_to_sysreg(e) \
251 sys_reg(3, \
252 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
253 ESR_ELx_SYS64_ISS_OP1_SHIFT), \
254 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
255 ESR_ELx_SYS64_ISS_CRN_SHIFT), \
256 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
257 ESR_ELx_SYS64_ISS_CRM_SHIFT), \
258 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
259 ESR_ELx_SYS64_ISS_OP2_SHIFT))
260
261 /*
262 * ISS field definitions for floating-point exception traps
263 * (FP_EXC_32/FP_EXC_64).
264 *
265 * (The FPEXC_* constants are used instead for common bits.)
266 */
267
268 #define ESR_ELx_FP_EXC_TFV (UL(1) << 23)
269
270 /*
271 * ISS field definitions for CP15 accesses
272 */
273 #define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1
274 #define ESR_ELx_CP15_32_ISS_DIR_READ 0x1
275 #define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0
276
277 #define ESR_ELx_CP15_32_ISS_RT_SHIFT 5
278 #define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
279 #define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1
280 #define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
281 #define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10
282 #define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
283 #define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14
284 #define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
285 #define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17
286 #define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
287
288 #define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \
289 ESR_ELx_CP15_32_ISS_OP2_MASK | \
290 ESR_ELx_CP15_32_ISS_CRN_MASK | \
291 ESR_ELx_CP15_32_ISS_CRM_MASK | \
292 ESR_ELx_CP15_32_ISS_DIR_MASK)
293 #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
294 (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
295 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
296 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
297 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
298
299 #define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1
300 #define ESR_ELx_CP15_64_ISS_DIR_READ 0x1
301 #define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0
302
303 #define ESR_ELx_CP15_64_ISS_RT_SHIFT 5
304 #define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
305
306 #define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10
307 #define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
308
309 #define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16
310 #define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
311 #define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1
312 #define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
313
314 #define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
315 (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
316 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
317
318 #define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \
319 ESR_ELx_CP15_64_ISS_CRM_MASK | \
320 ESR_ELx_CP15_64_ISS_DIR_MASK)
321
322 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
323 ESR_ELx_CP15_64_ISS_DIR_READ)
324
325 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \
326 ESR_ELx_CP15_64_ISS_DIR_READ)
327
328 #define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
329 ESR_ELx_CP15_32_ISS_DIR_READ)
330
331 #ifndef __ASSEMBLY__
332 #include <asm/types.h>
333
esr_is_data_abort(u32 esr)334 static inline bool esr_is_data_abort(u32 esr)
335 {
336 const u32 ec = ESR_ELx_EC(esr);
337
338 return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;
339 }
340
341 const char *esr_get_class_string(u32 esr);
342 #endif /* __ASSEMBLY */
343
344 #endif /* __ASM_ESR_H */
345