1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Clock setup for SMDK5250 board based on EXYNOS5
4 *
5 * Copyright (C) 2012 Samsung Electronics
6 */
7
8 #include <config.h>
9 #include <asm/io.h>
10 #include <asm/arch/clk.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/spl.h>
13 #include <asm/arch/dwmmc.h>
14
15 #include "clock_init.h"
16 #include "common_setup.h"
17 #include "exynos5_setup.h"
18
19 #define FSYS1_MMC0_DIV_MASK 0xff0f
20 #define FSYS1_MMC0_DIV_VAL 0x0701
21
22 struct arm_clk_ratios arm_clk_ratios[] = {
23 #ifdef CONFIG_EXYNOS5420
24 {
25 .arm_freq_mhz = 900,
26
27 .apll_mdiv = 0x96,
28 .apll_pdiv = 0x2,
29 .apll_sdiv = 0x1,
30
31 .arm2_ratio = 0x0,
32 .apll_ratio = 0x3,
33 .pclk_dbg_ratio = 0x6,
34 .atb_ratio = 0x6,
35 .periph_ratio = 0x7,
36 .acp_ratio = 0x0,
37 .cpud_ratio = 0x2,
38 .arm_ratio = 0x0,
39 }
40 #else
41 {
42 .arm_freq_mhz = 600,
43
44 .apll_mdiv = 0xc8,
45 .apll_pdiv = 0x4,
46 .apll_sdiv = 0x1,
47
48 .arm2_ratio = 0x0,
49 .apll_ratio = 0x1,
50 .pclk_dbg_ratio = 0x1,
51 .atb_ratio = 0x2,
52 .periph_ratio = 0x7,
53 .acp_ratio = 0x7,
54 .cpud_ratio = 0x1,
55 .arm_ratio = 0x0,
56 }, {
57 .arm_freq_mhz = 800,
58
59 .apll_mdiv = 0x64,
60 .apll_pdiv = 0x3,
61 .apll_sdiv = 0x0,
62
63 .arm2_ratio = 0x0,
64 .apll_ratio = 0x1,
65 .pclk_dbg_ratio = 0x1,
66 .atb_ratio = 0x3,
67 .periph_ratio = 0x7,
68 .acp_ratio = 0x7,
69 .cpud_ratio = 0x2,
70 .arm_ratio = 0x0,
71 }, {
72 .arm_freq_mhz = 1000,
73
74 .apll_mdiv = 0x7d,
75 .apll_pdiv = 0x3,
76 .apll_sdiv = 0x0,
77
78 .arm2_ratio = 0x0,
79 .apll_ratio = 0x1,
80 .pclk_dbg_ratio = 0x1,
81 .atb_ratio = 0x4,
82 .periph_ratio = 0x7,
83 .acp_ratio = 0x7,
84 .cpud_ratio = 0x2,
85 .arm_ratio = 0x0,
86 }, {
87 .arm_freq_mhz = 1200,
88
89 .apll_mdiv = 0x96,
90 .apll_pdiv = 0x3,
91 .apll_sdiv = 0x0,
92
93 .arm2_ratio = 0x0,
94 .apll_ratio = 0x3,
95 .pclk_dbg_ratio = 0x1,
96 .atb_ratio = 0x5,
97 .periph_ratio = 0x7,
98 .acp_ratio = 0x7,
99 .cpud_ratio = 0x3,
100 .arm_ratio = 0x0,
101 }, {
102 .arm_freq_mhz = 1400,
103
104 .apll_mdiv = 0xaf,
105 .apll_pdiv = 0x3,
106 .apll_sdiv = 0x0,
107
108 .arm2_ratio = 0x0,
109 .apll_ratio = 0x3,
110 .pclk_dbg_ratio = 0x1,
111 .atb_ratio = 0x6,
112 .periph_ratio = 0x7,
113 .acp_ratio = 0x7,
114 .cpud_ratio = 0x3,
115 .arm_ratio = 0x0,
116 }, {
117 .arm_freq_mhz = 1700,
118
119 .apll_mdiv = 0x1a9,
120 .apll_pdiv = 0x6,
121 .apll_sdiv = 0x0,
122
123 .arm2_ratio = 0x0,
124 .apll_ratio = 0x3,
125 .pclk_dbg_ratio = 0x1,
126 .atb_ratio = 0x6,
127 .periph_ratio = 0x7,
128 .acp_ratio = 0x7,
129 .cpud_ratio = 0x3,
130 .arm_ratio = 0x0,
131 }
132 #endif
133 };
134
135 struct mem_timings mem_timings[] = {
136 #ifdef CONFIG_EXYNOS5420
137 {
138 .mem_manuf = MEM_MANUF_SAMSUNG,
139 .mem_type = DDR_MODE_DDR3,
140 .frequency_mhz = 800,
141
142 /* MPLL @800MHz*/
143 .mpll_mdiv = 0xc8,
144 .mpll_pdiv = 0x3,
145 .mpll_sdiv = 0x1,
146 /* CPLL @666MHz */
147 .cpll_mdiv = 0xde,
148 .cpll_pdiv = 0x4,
149 .cpll_sdiv = 0x1,
150 /* EPLL @600MHz */
151 .epll_mdiv = 0x64,
152 .epll_pdiv = 0x2,
153 .epll_sdiv = 0x1,
154 /* VPLL @430MHz */
155 .vpll_mdiv = 0xd7,
156 .vpll_pdiv = 0x3,
157 .vpll_sdiv = 0x2,
158 /* BPLL @800MHz */
159 .bpll_mdiv = 0xc8,
160 .bpll_pdiv = 0x3,
161 .bpll_sdiv = 0x1,
162 /* KPLL @600MHz */
163 .kpll_mdiv = 0x190,
164 .kpll_pdiv = 0x4,
165 .kpll_sdiv = 0x2,
166 /* DPLL @600MHz */
167 .dpll_mdiv = 0x190,
168 .dpll_pdiv = 0x4,
169 .dpll_sdiv = 0x2,
170 /* IPLL @370MHz */
171 .ipll_mdiv = 0xb9,
172 .ipll_pdiv = 0x3,
173 .ipll_sdiv = 0x2,
174 /* SPLL @400MHz */
175 .spll_mdiv = 0xc8,
176 .spll_pdiv = 0x3,
177 .spll_sdiv = 0x2,
178 /* RPLL @141Mhz */
179 .rpll_mdiv = 0x5E,
180 .rpll_pdiv = 0x2,
181 .rpll_sdiv = 0x3,
182
183 .direct_cmd_msr = {
184 0x00020018, 0x00030000, 0x00010046, 0x00000d70,
185 0x00000c70
186 },
187 .timing_ref = 0x000000bb,
188 .timing_row = 0x6836650f,
189 .timing_data = 0x3630580b,
190 .timing_power = 0x41000a26,
191 .phy0_dqs = 0x08080808,
192 .phy1_dqs = 0x08080808,
193 .phy0_dq = 0x08080808,
194 .phy1_dq = 0x08080808,
195 .phy0_tFS = 0x8,
196 .phy1_tFS = 0x8,
197 .phy0_pulld_dqs = 0xf,
198 .phy1_pulld_dqs = 0xf,
199
200 .lpddr3_ctrl_phy_reset = 0x1,
201 .ctrl_start_point = 0x10,
202 .ctrl_inc = 0x10,
203 .ctrl_start = 0x1,
204 .ctrl_dll_on = 0x1,
205 .ctrl_ref = 0x8,
206
207 .ctrl_force = 0x1a,
208 .ctrl_rdlat = 0x0b,
209 .ctrl_bstlen = 0x08,
210
211 .fp_resync = 0x8,
212 .iv_size = 0x7,
213 .dfi_init_start = 1,
214 .aref_en = 1,
215
216 .rd_fetch = 0x3,
217
218 .zq_mode_dds = 0x7,
219 .zq_mode_term = 0x1,
220 .zq_mode_noterm = 1,
221
222 /*
223 * Dynamic Clock: Always Running
224 * Memory Burst length: 8
225 * Number of chips: 1
226 * Memory Bus width: 32 bit
227 * Memory Type: DDR3
228 * Additional Latancy for PLL: 0 Cycle
229 */
230 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
231 DMC_MEMCONTROL_DPWRDN_DISABLE |
232 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
233 DMC_MEMCONTROL_TP_DISABLE |
234 DMC_MEMCONTROL_DSREF_DISABLE |
235 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
236 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
237 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
238 DMC_MEMCONTROL_NUM_CHIP_1 |
239 DMC_MEMCONTROL_BL_8 |
240 DMC_MEMCONTROL_PZQ_DISABLE |
241 DMC_MEMCONTROL_MRR_BYTE_7_0,
242 .memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
243 DMC_MEMCONFIGX_CHIP_COL_10 |
244 DMC_MEMCONFIGX_CHIP_ROW_15 |
245 DMC_MEMCONFIGX_CHIP_BANK_8,
246 .prechconfig_tp_cnt = 0xff,
247 .dpwrdn_cyc = 0xff,
248 .dsref_cyc = 0xffff,
249 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
250 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
251 DMC_CONCONTROL_RD_FETCH_DISABLE |
252 DMC_CONCONTROL_EMPTY_DISABLE |
253 DMC_CONCONTROL_AREF_EN_DISABLE |
254 DMC_CONCONTROL_IO_PD_CON_DISABLE,
255 .dmc_channels = 1,
256 .chips_per_channel = 1,
257 .chips_to_configure = 1,
258 .send_zq_init = 1,
259 .gate_leveling_enable = 1,
260 .read_leveling_enable = 0,
261 }
262 #else
263 {
264 .mem_manuf = MEM_MANUF_ELPIDA,
265 .mem_type = DDR_MODE_DDR3,
266 .frequency_mhz = 800,
267 .mpll_mdiv = 0xc8,
268 .mpll_pdiv = 0x3,
269 .mpll_sdiv = 0x0,
270 .cpll_mdiv = 0xde,
271 .cpll_pdiv = 0x4,
272 .cpll_sdiv = 0x2,
273 .gpll_mdiv = 0x215,
274 .gpll_pdiv = 0xc,
275 .gpll_sdiv = 0x1,
276 .epll_mdiv = 0x60,
277 .epll_pdiv = 0x3,
278 .epll_sdiv = 0x3,
279 .vpll_mdiv = 0x96,
280 .vpll_pdiv = 0x3,
281 .vpll_sdiv = 0x2,
282
283 .bpll_mdiv = 0x64,
284 .bpll_pdiv = 0x3,
285 .bpll_sdiv = 0x0,
286 .pclk_cdrex_ratio = 0x5,
287 .direct_cmd_msr = {
288 0x00020018, 0x00030000, 0x00010042, 0x00000d70
289 },
290 .timing_ref = 0x000000bb,
291 .timing_row = 0x8c36650e,
292 .timing_data = 0x3630580b,
293 .timing_power = 0x41000a44,
294 .phy0_dqs = 0x08080808,
295 .phy1_dqs = 0x08080808,
296 .phy0_dq = 0x08080808,
297 .phy1_dq = 0x08080808,
298 .phy0_tFS = 0x4,
299 .phy1_tFS = 0x4,
300 .phy0_pulld_dqs = 0xf,
301 .phy1_pulld_dqs = 0xf,
302
303 .lpddr3_ctrl_phy_reset = 0x1,
304 .ctrl_start_point = 0x10,
305 .ctrl_inc = 0x10,
306 .ctrl_start = 0x1,
307 .ctrl_dll_on = 0x1,
308 .ctrl_ref = 0x8,
309
310 .ctrl_force = 0x1a,
311 .ctrl_rdlat = 0x0b,
312 .ctrl_bstlen = 0x08,
313
314 .fp_resync = 0x8,
315 .iv_size = 0x7,
316 .dfi_init_start = 1,
317 .aref_en = 1,
318
319 .rd_fetch = 0x3,
320
321 .zq_mode_dds = 0x7,
322 .zq_mode_term = 0x1,
323 .zq_mode_noterm = 0,
324
325 /*
326 * Dynamic Clock: Always Running
327 * Memory Burst length: 8
328 * Number of chips: 1
329 * Memory Bus width: 32 bit
330 * Memory Type: DDR3
331 * Additional Latancy for PLL: 0 Cycle
332 */
333 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
334 DMC_MEMCONTROL_DPWRDN_DISABLE |
335 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
336 DMC_MEMCONTROL_TP_DISABLE |
337 DMC_MEMCONTROL_DSREF_ENABLE |
338 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
339 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
340 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
341 DMC_MEMCONTROL_NUM_CHIP_1 |
342 DMC_MEMCONTROL_BL_8 |
343 DMC_MEMCONTROL_PZQ_DISABLE |
344 DMC_MEMCONTROL_MRR_BYTE_7_0,
345 .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
346 DMC_MEMCONFIGX_CHIP_COL_10 |
347 DMC_MEMCONFIGX_CHIP_ROW_15 |
348 DMC_MEMCONFIGX_CHIP_BANK_8,
349 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
350 .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
351 .prechconfig_tp_cnt = 0xff,
352 .dpwrdn_cyc = 0xff,
353 .dsref_cyc = 0xffff,
354 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
355 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
356 DMC_CONCONTROL_RD_FETCH_DISABLE |
357 DMC_CONCONTROL_EMPTY_DISABLE |
358 DMC_CONCONTROL_AREF_EN_DISABLE |
359 DMC_CONCONTROL_IO_PD_CON_DISABLE,
360 .dmc_channels = 2,
361 .chips_per_channel = 2,
362 .chips_to_configure = 1,
363 .send_zq_init = 1,
364 .impedance = IMP_OUTPUT_DRV_30_OHM,
365 .gate_leveling_enable = 0,
366 }, {
367 .mem_manuf = MEM_MANUF_SAMSUNG,
368 .mem_type = DDR_MODE_DDR3,
369 .frequency_mhz = 800,
370 .mpll_mdiv = 0xc8,
371 .mpll_pdiv = 0x3,
372 .mpll_sdiv = 0x0,
373 .cpll_mdiv = 0xde,
374 .cpll_pdiv = 0x4,
375 .cpll_sdiv = 0x2,
376 .gpll_mdiv = 0x215,
377 .gpll_pdiv = 0xc,
378 .gpll_sdiv = 0x1,
379 .epll_mdiv = 0x60,
380 .epll_pdiv = 0x3,
381 .epll_sdiv = 0x3,
382 .vpll_mdiv = 0x96,
383 .vpll_pdiv = 0x3,
384 .vpll_sdiv = 0x2,
385
386 .bpll_mdiv = 0x64,
387 .bpll_pdiv = 0x3,
388 .bpll_sdiv = 0x0,
389 .pclk_cdrex_ratio = 0x5,
390 .direct_cmd_msr = {
391 0x00020018, 0x00030000, 0x00010000, 0x00000d70
392 },
393 .timing_ref = 0x000000bb,
394 .timing_row = 0x8c36650e,
395 .timing_data = 0x3630580b,
396 .timing_power = 0x41000a44,
397 .phy0_dqs = 0x08080808,
398 .phy1_dqs = 0x08080808,
399 .phy0_dq = 0x08080808,
400 .phy1_dq = 0x08080808,
401 .phy0_tFS = 0x8,
402 .phy1_tFS = 0x8,
403 .phy0_pulld_dqs = 0xf,
404 .phy1_pulld_dqs = 0xf,
405
406 .lpddr3_ctrl_phy_reset = 0x1,
407 .ctrl_start_point = 0x10,
408 .ctrl_inc = 0x10,
409 .ctrl_start = 0x1,
410 .ctrl_dll_on = 0x1,
411 .ctrl_ref = 0x8,
412
413 .ctrl_force = 0x1a,
414 .ctrl_rdlat = 0x0b,
415 .ctrl_bstlen = 0x08,
416
417 .fp_resync = 0x8,
418 .iv_size = 0x7,
419 .dfi_init_start = 1,
420 .aref_en = 1,
421
422 .rd_fetch = 0x3,
423
424 .zq_mode_dds = 0x5,
425 .zq_mode_term = 0x1,
426 .zq_mode_noterm = 1,
427
428 /*
429 * Dynamic Clock: Always Running
430 * Memory Burst length: 8
431 * Number of chips: 1
432 * Memory Bus width: 32 bit
433 * Memory Type: DDR3
434 * Additional Latancy for PLL: 0 Cycle
435 */
436 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
437 DMC_MEMCONTROL_DPWRDN_DISABLE |
438 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
439 DMC_MEMCONTROL_TP_DISABLE |
440 DMC_MEMCONTROL_DSREF_ENABLE |
441 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
442 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
443 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
444 DMC_MEMCONTROL_NUM_CHIP_1 |
445 DMC_MEMCONTROL_BL_8 |
446 DMC_MEMCONTROL_PZQ_DISABLE |
447 DMC_MEMCONTROL_MRR_BYTE_7_0,
448 .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
449 DMC_MEMCONFIGX_CHIP_COL_10 |
450 DMC_MEMCONFIGX_CHIP_ROW_15 |
451 DMC_MEMCONFIGX_CHIP_BANK_8,
452 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
453 .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
454 .prechconfig_tp_cnt = 0xff,
455 .dpwrdn_cyc = 0xff,
456 .dsref_cyc = 0xffff,
457 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
458 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
459 DMC_CONCONTROL_RD_FETCH_DISABLE |
460 DMC_CONCONTROL_EMPTY_DISABLE |
461 DMC_CONCONTROL_AREF_EN_DISABLE |
462 DMC_CONCONTROL_IO_PD_CON_DISABLE,
463 .dmc_channels = 2,
464 .chips_per_channel = 2,
465 .chips_to_configure = 1,
466 .send_zq_init = 1,
467 .impedance = IMP_OUTPUT_DRV_40_OHM,
468 .gate_leveling_enable = 1,
469 }
470 #endif
471 };
472
473 /**
474 * Get the required memory type and speed (SPL version).
475 *
476 * In SPL we have no device tree, so we use the machine parameters
477 *
478 * @param mem_type Returns memory type
479 * @param frequency_mhz Returns memory speed in MHz
480 * @param arm_freq Returns ARM clock speed in MHz
481 * @param mem_manuf Return Memory Manufacturer name
482 */
clock_get_mem_selection(enum ddr_mode * mem_type,unsigned * frequency_mhz,unsigned * arm_freq,enum mem_manuf * mem_manuf)483 static void clock_get_mem_selection(enum ddr_mode *mem_type,
484 unsigned *frequency_mhz, unsigned *arm_freq,
485 enum mem_manuf *mem_manuf)
486 {
487 struct spl_machine_param *params;
488
489 params = spl_get_machine_params();
490 *mem_type = params->mem_type;
491 *frequency_mhz = params->frequency_mhz;
492 *arm_freq = params->arm_freq_mhz;
493 *mem_manuf = params->mem_manuf;
494 }
495
496 /* Get the ratios for setting ARM clock */
get_arm_ratios(void)497 struct arm_clk_ratios *get_arm_ratios(void)
498 {
499 struct arm_clk_ratios *arm_ratio;
500 enum ddr_mode mem_type;
501 enum mem_manuf mem_manuf;
502 unsigned frequency_mhz, arm_freq;
503 int i;
504
505 clock_get_mem_selection(&mem_type, &frequency_mhz,
506 &arm_freq, &mem_manuf);
507
508 for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
509 i++, arm_ratio++) {
510 if (arm_ratio->arm_freq_mhz == arm_freq)
511 return arm_ratio;
512 }
513
514 /* will hang if failed to find clock ratio */
515 while (1)
516 ;
517
518 return NULL;
519 }
520
clock_get_mem_timings(void)521 struct mem_timings *clock_get_mem_timings(void)
522 {
523 struct mem_timings *mem;
524 enum ddr_mode mem_type;
525 enum mem_manuf mem_manuf;
526 unsigned frequency_mhz, arm_freq;
527 int i;
528
529 clock_get_mem_selection(&mem_type, &frequency_mhz,
530 &arm_freq, &mem_manuf);
531 for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
532 i++, mem++) {
533 if (mem->mem_type == mem_type &&
534 mem->frequency_mhz == frequency_mhz &&
535 mem->mem_manuf == mem_manuf)
536 return mem;
537 }
538
539 /* will hang if failed to find memory timings */
540 while (1)
541 ;
542
543 return NULL;
544 }
545
exynos5250_system_clock_init(void)546 static void exynos5250_system_clock_init(void)
547 {
548 struct exynos5_clock *clk =
549 (struct exynos5_clock *)samsung_get_base_clock();
550 struct mem_timings *mem;
551 struct arm_clk_ratios *arm_clk_ratio;
552 u32 val, tmp;
553
554 mem = clock_get_mem_timings();
555 arm_clk_ratio = get_arm_ratios();
556
557 clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK);
558 do {
559 val = readl(&clk->mux_stat_cpu);
560 } while ((val | MUX_APLL_SEL_MASK) != val);
561
562 clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK);
563 do {
564 val = readl(&clk->mux_stat_core1);
565 } while ((val | MUX_MPLL_SEL_MASK) != val);
566
567 clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
568 clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
569 clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
570 clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
571 tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
572 | MUX_GPLL_SEL_MASK;
573 do {
574 val = readl(&clk->mux_stat_top2);
575 } while ((val | tmp) != val);
576
577 clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK);
578 do {
579 val = readl(&clk->mux_stat_cdrex);
580 } while ((val | MUX_BPLL_SEL_MASK) != val);
581
582 /* PLL locktime */
583 writel(mem->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
584 writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
585 writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
586 writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
587 writel(mem->gpll_pdiv * PLL_X_LOCK_FACTOR, &clk->gpll_lock);
588 writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
589 writel(mem->vpll_pdiv * PLL_X_LOCK_FACTOR, &clk->vpll_lock);
590
591 writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
592
593 writel(MUX_HPM_SEL_MASK, &clk->src_cpu);
594 do {
595 val = readl(&clk->mux_stat_cpu);
596 } while ((val | HPM_SEL_SCLK_MPLL) != val);
597
598 val = arm_clk_ratio->arm2_ratio << 28
599 | arm_clk_ratio->apll_ratio << 24
600 | arm_clk_ratio->pclk_dbg_ratio << 20
601 | arm_clk_ratio->atb_ratio << 16
602 | arm_clk_ratio->periph_ratio << 12
603 | arm_clk_ratio->acp_ratio << 8
604 | arm_clk_ratio->cpud_ratio << 4
605 | arm_clk_ratio->arm_ratio;
606 writel(val, &clk->div_cpu0);
607 do {
608 val = readl(&clk->div_stat_cpu0);
609 } while (0 != val);
610
611 writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
612 do {
613 val = readl(&clk->div_stat_cpu1);
614 } while (0 != val);
615
616 /* Set APLL */
617 writel(APLL_CON1_VAL, &clk->apll_con1);
618 val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
619 arm_clk_ratio->apll_sdiv);
620 writel(val, &clk->apll_con0);
621 while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
622 ;
623
624 /* Set MPLL */
625 writel(MPLL_CON1_VAL, &clk->mpll_con1);
626 val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
627 writel(val, &clk->mpll_con0);
628 while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
629 ;
630
631 /* Set BPLL */
632 writel(BPLL_CON1_VAL, &clk->bpll_con1);
633 val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
634 writel(val, &clk->bpll_con0);
635 while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
636 ;
637
638 /* Set CPLL */
639 writel(CPLL_CON1_VAL, &clk->cpll_con1);
640 val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
641 writel(val, &clk->cpll_con0);
642 while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
643 ;
644
645 /* Set GPLL */
646 writel(GPLL_CON1_VAL, &clk->gpll_con1);
647 val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
648 writel(val, &clk->gpll_con0);
649 while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
650 ;
651
652 /* Set EPLL */
653 writel(EPLL_CON2_VAL, &clk->epll_con2);
654 writel(EPLL_CON1_VAL, &clk->epll_con1);
655 val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
656 writel(val, &clk->epll_con0);
657 while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
658 ;
659
660 /* Set VPLL */
661 writel(VPLL_CON2_VAL, &clk->vpll_con2);
662 writel(VPLL_CON1_VAL, &clk->vpll_con1);
663 val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
664 writel(val, &clk->vpll_con0);
665 while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
666 ;
667
668 writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
669 writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
670 while (readl(&clk->div_stat_core0) != 0)
671 ;
672
673 writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
674 while (readl(&clk->div_stat_core1) != 0)
675 ;
676
677 writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt);
678 while (readl(&clk->div_stat_sysrgt) != 0)
679 ;
680
681 writel(CLK_DIV_ACP_VAL, &clk->div_acp);
682 while (readl(&clk->div_stat_acp) != 0)
683 ;
684
685 writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft);
686 while (readl(&clk->div_stat_syslft) != 0)
687 ;
688
689 writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
690 writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
691 writel(TOP2_VAL, &clk->src_top2);
692 writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
693
694 writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
695 while (readl(&clk->div_stat_top0))
696 ;
697
698 writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
699 while (readl(&clk->div_stat_top1))
700 ;
701
702 writel(CLK_SRC_LEX_VAL, &clk->src_lex);
703 while (1) {
704 val = readl(&clk->mux_stat_lex);
705 if (val == (val | 1))
706 break;
707 }
708
709 writel(CLK_DIV_LEX_VAL, &clk->div_lex);
710 while (readl(&clk->div_stat_lex))
711 ;
712
713 writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
714 while (readl(&clk->div_stat_r0x))
715 ;
716
717 writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
718 while (readl(&clk->div_stat_r0x))
719 ;
720
721 writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
722 while (readl(&clk->div_stat_r1x))
723 ;
724
725 writel(CLK_REG_DISABLE, &clk->src_cdrex);
726
727 writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
728 while (readl(&clk->div_stat_cdrex))
729 ;
730
731 val = readl(&clk->src_cpu);
732 val |= CLK_SRC_CPU_VAL;
733 writel(val, &clk->src_cpu);
734
735 val = readl(&clk->src_top2);
736 val |= CLK_SRC_TOP2_VAL;
737 writel(val, &clk->src_top2);
738
739 val = readl(&clk->src_core1);
740 val |= CLK_SRC_CORE1_VAL;
741 writel(val, &clk->src_core1);
742
743 writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
744 writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
745 while (readl(&clk->div_stat_fsys0))
746 ;
747
748 writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu);
749 writel(CLK_REG_DISABLE, &clk->clkout_cmu_core);
750 writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp);
751 writel(CLK_REG_DISABLE, &clk->clkout_cmu_top);
752 writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex);
753 writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
754 writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
755 writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
756
757 writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
758 writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
759
760 writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
761 writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
762 writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
763 writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
764
765 writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp);
766 writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp);
767 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
768 writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
769 writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
770
771 /* FIMD1 SRC CLK SELECTION */
772 writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0);
773
774 val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
775 | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
776 | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
777 | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
778 writel(val, &clk->div_fsys2);
779 }
780
exynos5420_system_clock_init(void)781 static void exynos5420_system_clock_init(void)
782 {
783 struct exynos5420_clock *clk =
784 (struct exynos5420_clock *)samsung_get_base_clock();
785 struct mem_timings *mem;
786 struct arm_clk_ratios *arm_clk_ratio;
787 u32 val;
788
789 mem = clock_get_mem_timings();
790 arm_clk_ratio = get_arm_ratios();
791
792 /* PLL locktime */
793 writel(arm_clk_ratio->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
794 writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
795 writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
796 writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
797 writel(mem->dpll_pdiv * PLL_LOCK_FACTOR, &clk->dpll_lock);
798 writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
799 writel(mem->vpll_pdiv * PLL_LOCK_FACTOR, &clk->vpll_lock);
800 writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
801 writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
802 writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
803 writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock);
804
805 setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
806
807 writel(0, &clk->src_top6);
808
809 writel(0, &clk->src_cdrex);
810 writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
811 writel(HPM_RATIO, &clk->div_cpu1);
812 writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
813
814 /* switch A15 clock source to OSC clock before changing APLL */
815 clrbits_le32(&clk->src_cpu, APLL_FOUT);
816
817 /* Set APLL */
818 writel(APLL_CON1_VAL, &clk->apll_con1);
819 val = set_pll(arm_clk_ratio->apll_mdiv,
820 arm_clk_ratio->apll_pdiv,
821 arm_clk_ratio->apll_sdiv);
822 writel(val, &clk->apll_con0);
823 while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0)
824 ;
825
826 /* now it is safe to switch to APLL */
827 setbits_le32(&clk->src_cpu, APLL_FOUT);
828
829 writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
830 writel(CLK_DIV_KFC_VAL, &clk->div_kfc0);
831
832 /* switch A7 clock source to OSC clock before changing KPLL */
833 clrbits_le32(&clk->src_kfc, KPLL_FOUT);
834
835 /* Set KPLL*/
836 writel(KPLL_CON1_VAL, &clk->kpll_con1);
837 val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv);
838 writel(val, &clk->kpll_con0);
839 while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
840 ;
841
842 /* now it is safe to switch to KPLL */
843 setbits_le32(&clk->src_kfc, KPLL_FOUT);
844
845 /* Set MPLL */
846 writel(MPLL_CON1_VAL, &clk->mpll_con1);
847 val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
848 writel(val, &clk->mpll_con0);
849 while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0)
850 ;
851
852 /* Set DPLL */
853 writel(DPLL_CON1_VAL, &clk->dpll_con1);
854 val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv);
855 writel(val, &clk->dpll_con0);
856 while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0)
857 ;
858
859 /* Set EPLL */
860 writel(EPLL_CON2_VAL, &clk->epll_con2);
861 writel(EPLL_CON1_VAL, &clk->epll_con1);
862 val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
863 writel(val, &clk->epll_con0);
864 while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0)
865 ;
866
867 /* Set CPLL */
868 writel(CPLL_CON1_VAL, &clk->cpll_con1);
869 val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
870 writel(val, &clk->cpll_con0);
871 while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0)
872 ;
873
874 /* Set IPLL */
875 writel(IPLL_CON1_VAL, &clk->ipll_con1);
876 val = set_pll(mem->ipll_mdiv, mem->ipll_pdiv, mem->ipll_sdiv);
877 writel(val, &clk->ipll_con0);
878 while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0)
879 ;
880
881 /* Set VPLL */
882 writel(VPLL_CON1_VAL, &clk->vpll_con1);
883 val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
884 writel(val, &clk->vpll_con0);
885 while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0)
886 ;
887
888 /* Set BPLL */
889 writel(BPLL_CON1_VAL, &clk->bpll_con1);
890 val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
891 writel(val, &clk->bpll_con0);
892 while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0)
893 ;
894
895 /* Set SPLL */
896 writel(SPLL_CON1_VAL, &clk->spll_con1);
897 val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv);
898 writel(val, &clk->spll_con0);
899 while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
900 ;
901
902 /* Set RPLL */
903 writel(RPLL_CON2_VAL, &clk->rpll_con2);
904 writel(RPLL_CON1_VAL, &clk->rpll_con1);
905 val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv);
906 writel(val, &clk->rpll_con0);
907 while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0)
908 ;
909
910 writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
911 writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
912
913 writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
914 writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
915 writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
916 writel(CLK_SRC_TOP7_VAL, &clk->src_top7);
917
918 writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
919 writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
920 writel(CLK_DIV_TOP2_VAL, &clk->div_top2);
921
922 writel(0, &clk->src_top10);
923 writel(0, &clk->src_top11);
924 writel(0, &clk->src_top12);
925
926 writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
927 writel(CLK_SRC_TOP4_VAL, &clk->src_top4);
928 writel(CLK_SRC_TOP5_VAL, &clk->src_top5);
929
930 /* DISP1 BLK CLK SELECTION */
931 writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10);
932 writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10);
933
934 /* AUDIO BLK */
935 writel(AUDIO0_SEL_EPLL, &clk->src_mau);
936 writel(DIV_MAU_VAL, &clk->div_mau);
937
938 /* FSYS */
939 writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
940 writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
941 writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
942 writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
943
944 writel(CLK_SRC_ISP_VAL, &clk->src_isp);
945 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
946 writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
947
948 writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
949 writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
950
951 writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
952 writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
953 writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
954 writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
955 writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4);
956
957 writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1);
958
959 writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
960 writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
961 writel(CLK_DIV_G2D, &clk->div_g2d);
962
963 writel(CLK_SRC_TOP6_VAL, &clk->src_top6);
964 writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
965 writel(CLK_SRC_KFC_VAL, &clk->src_kfc);
966 }
967
system_clock_init(void)968 void system_clock_init(void)
969 {
970 if (proid_is_exynos542x())
971 exynos5420_system_clock_init();
972 else
973 exynos5250_system_clock_init();
974 }
975
clock_init_dp_clock(void)976 void clock_init_dp_clock(void)
977 {
978 struct exynos5_clock *clk =
979 (struct exynos5_clock *)samsung_get_base_clock();
980
981 /* DP clock enable */
982 setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
983
984 /* We run DP at 267 Mhz */
985 setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
986 }
987
988 /*
989 * Set clock divisor value for booting from EMMC.
990 * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz.
991 */
emmc_boot_clk_div_set(void)992 void emmc_boot_clk_div_set(void)
993 {
994 struct exynos5_clock *clk =
995 (struct exynos5_clock *)samsung_get_base_clock();
996 unsigned int div_mmc;
997
998 div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK;
999 div_mmc |= FSYS1_MMC0_DIV_VAL;
1000 writel(div_mmc, (unsigned int) &clk->div_fsys1);
1001 }
1002