1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2012 Samsung Electronics 4 * Donghwa Lee <dh09.lee@samsung.com> 5 */ 6 7 #ifndef __ASM_ARM_ARCH_SYSTEM_H_ 8 #define __ASM_ARM_ARCH_SYSTEM_H_ 9 10 #ifndef __ASSEMBLY__ 11 struct exynos4_sysreg { 12 unsigned char res1[0x210]; 13 unsigned int display_ctrl; 14 unsigned int display_ctrl2; 15 unsigned int camera_control; 16 unsigned int audio_endian; 17 unsigned int jtag_con; 18 }; 19 20 struct exynos5_sysreg { 21 unsigned char res1[0x214]; 22 unsigned int disp1blk_cfg; 23 unsigned int disp2blk_cfg; 24 unsigned int hdcp_e_fuse; 25 unsigned int gsclblk_cfg0; 26 unsigned int gsclblk_cfg1; 27 unsigned int reserved; 28 unsigned int ispblk_cfg; 29 unsigned int usb20phy_cfg; 30 unsigned char res2[0x29c]; 31 unsigned int mipi_dphy; 32 unsigned int dptx_dphy; 33 unsigned int phyclk_sel; 34 }; 35 #endif 36 37 #define USB20_PHY_CFG_HOST_LINK_EN (1 << 0) 38 39 /* Move 0xd3 value to CPSR register to enable SVC mode */ 40 #define svc32_mode_en() __asm__ __volatile__ \ 41 ("@ I&F disable, Mode: 0x13 - SVC\n\t" \ 42 "msr cpsr_c, %0\n\t" : : "r"(0x13|0xC0)) 43 44 /* Set program counter with the given value */ 45 #define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x)) 46 47 /* Branch to the given location */ 48 #define branch_bx(x) __asm__ __volatile__ ("bx %0\n\t" : : "r"(x)) 49 50 /* Read Main Id register */ 51 #define mrc_midr(x) __asm__ __volatile__ \ 52 ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(x) : ) 53 54 /* Read Multiprocessor Affinity Register */ 55 #define mrc_mpafr(x) __asm__ __volatile__ \ 56 ("mrc p15, 0, %0, c0, c0, 5\n\t" : "=r"(x) : ) 57 58 /* Read System Control Register */ 59 #define mrc_sctlr(x) __asm__ __volatile__ \ 60 ("mrc p15, 0, %0, c1, c0, 0\n\t" : "=r"(x) : ) 61 62 /* Read Auxiliary Control Register */ 63 #define mrc_auxr(x) __asm__ __volatile__ \ 64 ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(x) : ) 65 66 /* Read L2 Control register */ 67 #define mrc_l2_ctlr(x) __asm__ __volatile__ \ 68 ("mrc p15, 1, %0, c9, c0, 2\n\t" : "=r"(x) : ) 69 70 /* Read L2 Auxilliary Control register */ 71 #define mrc_l2_aux_ctlr(x) __asm__ __volatile__ \ 72 ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(x) : ) 73 74 /* Write System Control Register */ 75 #define mcr_sctlr(x) __asm__ __volatile__ \ 76 ("mcr p15, 0, %0, c1, c0, 0\n\t" : : "r"(x)) 77 78 /* Write Auxiliary Control Register */ 79 #define mcr_auxr(x) __asm__ __volatile__ \ 80 ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(x)) 81 82 /* Invalidate all instruction caches to PoU */ 83 #define mcr_icache(x) __asm__ __volatile__ \ 84 ("mcr p15, 0, %0, c7, c5, 0\n\t" : : "r"(x)) 85 86 /* Invalidate unified TLB */ 87 #define mcr_tlb(x) __asm__ __volatile__ \ 88 ("mcr p15, 0, %0, c8, c7, 0\n\t" : : "r"(x)) 89 90 /* Write L2 Control register */ 91 #define mcr_l2_ctlr(x) __asm__ __volatile__ \ 92 ("mcr p15, 1, %0, c9, c0, 2\n\t" : : "r"(x)) 93 94 /* Write L2 Auxilliary Control register */ 95 #define mcr_l2_aux_ctlr(x) __asm__ __volatile__ \ 96 ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(x)) 97 98 void set_usbhost_mode(unsigned int mode); 99 void set_system_display_ctrl(void); 100 101 #endif /* _EXYNOS4_SYSTEM_H */ 102