1 /*
2 * Lowlevel setup for EXYNOS5 based board
3 *
4 * Copyright (C) 2013 Samsung Electronics
5 * Rajeshwari Shinde <rajeshwari.s@samsung.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26 #include <config.h>
27 #include <debug_uart.h>
28 #include <asm/system.h>
29 #include <init.h>
30 #include <asm/arch/cpu.h>
31 #include <asm/arch/dmc.h>
32 #include <asm/arch/power.h>
33 #include <asm/arch/tzpc.h>
34 #include <asm/arch/periph.h>
35 #include <asm/arch/pinmux.h>
36 #include <asm/arch/system.h>
37 #include <asm/armv7.h>
38 #include "common_setup.h"
39 #include "exynos5_setup.h"
40
41 /* These are the things we can do during low-level init */
42 enum {
43 DO_WAKEUP = 1 << 0,
44 DO_CLOCKS = 1 << 1,
45 DO_MEM_RESET = 1 << 2,
46 DO_UART = 1 << 3,
47 DO_POWER = 1 << 4,
48 };
49
50 #ifdef CONFIG_EXYNOS5420
51
52 /* Address for relocating helper code (Last 4 KB of IRAM) */
53 #define EXYNOS_RELOCATE_CODE_BASE (CFG_IRAM_TOP - 0x1000)
54
55 /*
56 * Power up secondary CPUs.
57 */
secondary_cpu_start(void)58 static void secondary_cpu_start(void)
59 {
60 v7_enable_smp(EXYNOS5420_INFORM_BASE);
61 svc32_mode_en();
62 branch_bx(EXYNOS_RELOCATE_CODE_BASE);
63 }
64
65 /*
66 * This is the entry point of hotplug-in and
67 * cluster switching.
68 */
low_power_start(void)69 static void low_power_start(void)
70 {
71 uint32_t val, reg_val;
72
73 reg_val = readl(EXYNOS5420_SPARE_BASE);
74 if (reg_val != CPU_RST_FLAG_VAL) {
75 writel(0x0, CFG_LOWPOWER_FLAG);
76 branch_bx(0x0);
77 }
78
79 reg_val = readl(CFG_PHY_IRAM_BASE + 0x4);
80 if (reg_val != (uint32_t)&low_power_start) {
81 /* Store jump address as low_power_start if not present */
82 writel((uint32_t)&low_power_start, CFG_PHY_IRAM_BASE + 0x4);
83 dsb();
84 sev();
85 }
86
87 /* Set the CPU to SVC32 mode */
88 svc32_mode_en();
89
90 #ifndef CONFIG_SYS_L2CACHE_OFF
91 /* Read MIDR for Primary Part Number */
92 mrc_midr(val);
93 val = (val >> 4);
94 val &= 0xf;
95
96 if (val == 0xf) {
97 configure_l2_ctlr();
98 configure_l2_actlr();
99 v7_enable_l2_hazard_detect();
100 }
101 #endif
102
103 /* Invalidate L1 & TLB */
104 val = 0x0;
105 mcr_tlb(val);
106 mcr_icache(val);
107
108 /* Disable MMU stuff and caches */
109 mrc_sctlr(val);
110
111 val &= ~((0x2 << 12) | 0x7);
112 val |= ((0x1 << 12) | (0x8 << 8) | 0x2);
113 mcr_sctlr(val);
114
115 /* CPU state is hotplug or reset */
116 secondary_cpu_start();
117
118 /* Core should not enter into WFI here */
119 wfi();
120 }
121
122 /*
123 * Pointer to this function is stored in iRam which is used
124 * for jump and power down of a specific core.
125 */
power_down_core(void)126 static void power_down_core(void)
127 {
128 uint32_t tmp, core_id, core_config;
129
130 /* Get the unique core id */
131 /*
132 * Multiprocessor Affinity Register
133 * [11:8] Cluster ID
134 * [1:0] CPU ID
135 */
136 mrc_mpafr(core_id);
137 tmp = core_id & 0x3;
138 core_id = (core_id >> 6) & ~3;
139 core_id |= tmp;
140 core_id &= 0x3f;
141
142 /* Set the status of the core to low */
143 core_config = (core_id * CPU_CONFIG_STATUS_OFFSET);
144 core_config += EXYNOS5420_CPU_CONFIG_BASE;
145 writel(0x0, core_config);
146
147 /* Core enter WFI */
148 wfi();
149 }
150
151 /*
152 * Configurations for secondary cores are inapt at this stage.
153 * Reconfigure secondary cores. Shutdown and change the status
154 * of all cores except the primary core.
155 */
secondary_cores_configure(void)156 static void secondary_cores_configure(void)
157 {
158 /* Clear secondary boot iRAM base */
159 writel(0x0, (EXYNOS_RELOCATE_CODE_BASE + 0x1C));
160
161 /* set lowpower flag and address */
162 writel(CPU_RST_FLAG_VAL, CFG_LOWPOWER_FLAG);
163 writel((uint32_t)&low_power_start, CFG_LOWPOWER_ADDR);
164 writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE);
165 /* Store jump address for power down */
166 writel((uint32_t)&power_down_core, CFG_PHY_IRAM_BASE + 0x4);
167
168 /* Need all core power down check */
169 dsb();
170 sev();
171 }
172
173 extern void relocate_wait_code(void);
174 #endif
175
do_lowlevel_init(void)176 int do_lowlevel_init(void)
177 {
178 uint32_t reset_status;
179 int actions = 0;
180
181 arch_cpu_init();
182
183 #if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420)
184 /*
185 * Init L2 cache parameters here for use by boot and resume
186 *
187 * These are here instead of in v7_outer_cache_enable() so that the
188 * L2 cache settings get properly set even at resume time or if we're
189 * running U-Boot with the cache off. The kernel still needs us to
190 * set these for it.
191 */
192 configure_l2_ctlr();
193 configure_l2_actlr();
194 dsb();
195 isb();
196
197 relocate_wait_code();
198
199 /* Reconfigure secondary cores */
200 secondary_cores_configure();
201 #endif
202
203 reset_status = get_reset_status();
204
205 switch (reset_status) {
206 case S5P_CHECK_SLEEP:
207 actions = DO_CLOCKS | DO_WAKEUP;
208 break;
209 case S5P_CHECK_DIDLE:
210 case S5P_CHECK_LPA:
211 actions = DO_WAKEUP;
212 break;
213 default:
214 /* This is a normal boot (not a wake from sleep) */
215 actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER;
216 }
217
218 if (actions & DO_POWER)
219 set_ps_hold_ctrl();
220
221 if (actions & DO_CLOCKS) {
222 system_clock_init();
223 #ifdef CONFIG_DEBUG_UART
224 #if (defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_SERIAL)) || \
225 !defined(CONFIG_XPL_BUILD)
226 exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
227 debug_uart_init();
228 #endif
229 #endif
230 mem_ctrl_init(actions & DO_MEM_RESET);
231 tzpc_init();
232 }
233
234 return actions & DO_WAKEUP;
235 }
236