1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007
4 * Sascha Hauer, Pengutronix
5 *
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 */
8
9 #include <bootm.h>
10 #include <dm.h>
11 #include <init.h>
12 #include <log.h>
13 #include <net.h>
14 #include <netdev.h>
15 #include <linux/errno.h>
16 #include <asm/io.h>
17 #include <asm/arch/imx-regs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/arch/crm_regs.h>
21 #include <asm/mach-imx/boot_mode.h>
22 #include <imx_thermal.h>
23 #include <ipu_pixfmt.h>
24 #include <thermal.h>
25 #include <sata.h>
26 #include <dm/device-internal.h>
27 #include <dm/uclass-internal.h>
28
29 #ifdef CONFIG_FSL_ESDHC_IMX
30 #include <fsl_esdhc_imx.h>
31 #endif
32
33 static u32 reset_cause = -1;
34
get_imx_reset_cause(void)35 u32 get_imx_reset_cause(void)
36 {
37 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
38
39 if (reset_cause == -1) {
40 reset_cause = readl(&src_regs->srsr);
41 /* preserve the value for U-Boot proper */
42 #if !defined(CONFIG_XPL_BUILD)
43 writel(reset_cause, &src_regs->srsr);
44 #endif
45 }
46
47 return reset_cause;
48 }
49
50 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD)
get_reset_cause(void)51 static char *get_reset_cause(void)
52 {
53 switch (get_imx_reset_cause()) {
54 case 0x00001:
55 case 0x00011:
56 return "POR";
57 case 0x00004:
58 return "CSU";
59 case 0x00008:
60 return "IPP USER";
61 case 0x00010:
62 #ifdef CONFIG_MX7
63 return "WDOG1";
64 #else
65 return "WDOG";
66 #endif
67 case 0x00020:
68 return "JTAG HIGH-Z";
69 case 0x00040:
70 return "JTAG SW";
71 case 0x00080:
72 return "WDOG3";
73 #ifdef CONFIG_MX7
74 case 0x00100:
75 return "WDOG4";
76 case 0x00200:
77 return "TEMPSENSE";
78 #elif defined(CONFIG_IMX8M)
79 case 0x00100:
80 return "WDOG2";
81 case 0x00200:
82 return "TEMPSENSE";
83 #else
84 case 0x00100:
85 return "TEMPSENSE";
86 case 0x10000:
87 return "WARM BOOT";
88 #endif
89 default:
90 return "unknown reset";
91 }
92 }
93 #endif
94
95 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD)
96
get_imx_type(u32 imxtype)97 const char *get_imx_type(u32 imxtype)
98 {
99 switch (imxtype) {
100 case MXC_CPU_IMX8MP:
101 return "8MP[8]"; /* Quad-core version of the imx8mp */
102 case MXC_CPU_IMX8MPD:
103 return "8MP Dual[3]"; /* Dual-core version of the imx8mp */
104 case MXC_CPU_IMX8MPL:
105 return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */
106 case MXC_CPU_IMX8MP6:
107 return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */
108 case MXC_CPU_IMX8MPUL:
109 return "8MP UltraLite"; /* Quad-core UltraLite version of the imx8mp */
110 case MXC_CPU_IMX8MN:
111 return "8MNano Quad"; /* Quad-core version */
112 case MXC_CPU_IMX8MND:
113 return "8MNano Dual"; /* Dual-core version */
114 case MXC_CPU_IMX8MNS:
115 return "8MNano Solo"; /* Single-core version */
116 case MXC_CPU_IMX8MNL:
117 return "8MNano QuadLite"; /* Quad-core Lite version */
118 case MXC_CPU_IMX8MNDL:
119 return "8MNano DualLite"; /* Dual-core Lite version */
120 case MXC_CPU_IMX8MNSL:
121 return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */
122 case MXC_CPU_IMX8MNUQ:
123 return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */
124 case MXC_CPU_IMX8MNUD:
125 return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */
126 case MXC_CPU_IMX8MNUS:
127 return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */
128 case MXC_CPU_IMX8MM:
129 return "8MMQ"; /* Quad-core version of the imx8mm */
130 case MXC_CPU_IMX8MML:
131 return "8MMQL"; /* Quad-core Lite version of the imx8mm */
132 case MXC_CPU_IMX8MMD:
133 return "8MMD"; /* Dual-core version of the imx8mm */
134 case MXC_CPU_IMX8MMDL:
135 return "8MMDL"; /* Dual-core Lite version of the imx8mm */
136 case MXC_CPU_IMX8MMS:
137 return "8MMS"; /* Single-core version of the imx8mm */
138 case MXC_CPU_IMX8MMSL:
139 return "8MMSL"; /* Single-core Lite version of the imx8mm */
140 case MXC_CPU_IMX8MQ:
141 return "8MQ"; /* Quad-core version of the imx8mq */
142 case MXC_CPU_IMX8MQL:
143 return "8MQLite"; /* Quad-core Lite version of the imx8mq */
144 case MXC_CPU_IMX8MD:
145 return "8MD"; /* Dual-core version of the imx8mq */
146 case MXC_CPU_MX7S:
147 return "7S"; /* Single-core version of the mx7 */
148 case MXC_CPU_MX7D:
149 return "7D"; /* Dual-core version of the mx7 */
150 case MXC_CPU_MX6QP:
151 return "6QP"; /* Quad-Plus version of the mx6 */
152 case MXC_CPU_MX6DP:
153 return "6DP"; /* Dual-Plus version of the mx6 */
154 case MXC_CPU_MX6Q:
155 return "6Q"; /* Quad-core version of the mx6 */
156 case MXC_CPU_MX6D:
157 return "6D"; /* Dual-core version of the mx6 */
158 case MXC_CPU_MX6DL:
159 return "6DL"; /* Dual Lite version of the mx6 */
160 case MXC_CPU_MX6SOLO:
161 return "6SOLO"; /* Solo version of the mx6 */
162 case MXC_CPU_MX6SL:
163 return "6SL"; /* Solo-Lite version of the mx6 */
164 case MXC_CPU_MX6SLL:
165 return "6SLL"; /* SLL version of the mx6 */
166 case MXC_CPU_MX6SX:
167 return "6SX"; /* SoloX version of the mx6 */
168 case MXC_CPU_MX6UL:
169 return "6UL"; /* Ultra-Lite version of the mx6 */
170 case MXC_CPU_MX6ULL:
171 return "6ULL"; /* ULL version of the mx6 */
172 case MXC_CPU_MX6ULZ:
173 return "6ULZ"; /* ULZ version of the mx6 */
174 case MXC_CPU_MX51:
175 return "51";
176 case MXC_CPU_MX53:
177 return "53";
178 default:
179 return "??";
180 }
181 }
182
print_cpuinfo(void)183 int print_cpuinfo(void)
184 {
185 u32 cpurev;
186 __maybe_unused u32 max_freq;
187
188 cpurev = get_cpu_rev();
189
190 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
191 struct udevice *thermal_dev;
192 int cpu_tmp, minc, maxc, ret;
193
194 printf("CPU: Freescale i.MX%s rev%d.%d",
195 get_imx_type((cpurev & 0x1FF000) >> 12),
196 (cpurev & 0x000F0) >> 4,
197 (cpurev & 0x0000F) >> 0);
198 max_freq = get_cpu_speed_grade_hz();
199 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
200 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
201 } else {
202 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
203 mxc_get_clock(MXC_ARM_CLK) / 1000000);
204 }
205 #else
206 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
207 get_imx_type((cpurev & 0x1FF000) >> 12),
208 (cpurev & 0x000F0) >> 4,
209 (cpurev & 0x0000F) >> 0,
210 mxc_get_clock(MXC_ARM_CLK) / 1000000);
211 #endif
212
213 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
214 puts("CPU: ");
215 switch (get_cpu_temp_grade(&minc, &maxc)) {
216 case TEMP_AUTOMOTIVE:
217 puts("Automotive temperature grade ");
218 break;
219 case TEMP_INDUSTRIAL:
220 puts("Industrial temperature grade ");
221 break;
222 case TEMP_EXTCOMMERCIAL:
223 puts("Extended Commercial temperature grade ");
224 break;
225 default:
226 puts("Commercial temperature grade ");
227 break;
228 }
229 printf("(%dC to %dC)", minc, maxc);
230 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
231 if (!ret) {
232 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
233
234 if (!ret)
235 printf(" at %dC", cpu_tmp);
236 else
237 debug(" - invalid sensor data\n");
238 } else {
239 debug(" - invalid sensor device\n");
240 }
241 puts("\n");
242 #endif
243
244 printf("Reset cause: %s\n", get_reset_cause());
245 return 0;
246 }
247 #endif
248
cpu_eth_init(struct bd_info * bis)249 int cpu_eth_init(struct bd_info *bis)
250 {
251 int rc = -ENODEV;
252
253 #if defined(CONFIG_FEC_MXC)
254 rc = fecmxc_initialize(bis);
255 #endif
256
257 return rc;
258 }
259
260 #ifdef CONFIG_FSL_ESDHC_IMX
261 /*
262 * Initializes on-chip MMC controllers.
263 * to override, implement board_mmc_init()
264 */
cpu_mmc_init(struct bd_info * bis)265 int cpu_mmc_init(struct bd_info *bis)
266 {
267 return fsl_esdhc_mmc_init(bis);
268 }
269 #endif
270
271 #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
get_ahb_clk(void)272 u32 get_ahb_clk(void)
273 {
274 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
275 u32 reg, ahb_podf;
276
277 reg = __raw_readl(&imx_ccm->cbcdr);
278 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
279 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
280
281 return get_periph_clk() / (ahb_podf + 1);
282 }
283 #endif
284
arch_preboot_os(void)285 void arch_preboot_os(void)
286 {
287 #if defined(CONFIG_IMX_AHCI)
288 struct udevice *dev;
289 int rc;
290
291 rc = uclass_find_device(UCLASS_AHCI, 0, &dev);
292 if (!rc && dev) {
293 rc = device_remove(dev, DM_REMOVE_NORMAL);
294 if (rc)
295 printf("Cannot remove SATA device '%s' (err=%d)\n",
296 dev->name, rc);
297 }
298 #endif
299
300 #if defined(CONFIG_SATA)
301 if (!is_mx6sdl()) {
302 sata_remove(0);
303 #if defined(CONFIG_MX6)
304 disable_sata_clock();
305 #endif
306 }
307 #endif
308 #if defined(CONFIG_VIDEO_IPUV3)
309 /* disable video before launching O/S */
310 ipuv3_fb_shutdown();
311 #endif
312 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_VIDEO)
313 lcdif_power_down();
314 #endif
315 }
316
317 #ifndef CONFIG_IMX8M
set_chipselect_size(int const cs_size)318 void set_chipselect_size(int const cs_size)
319 {
320 unsigned int reg;
321 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
322 reg = readl(&iomuxc_regs->gpr[1]);
323
324 switch (cs_size) {
325 case CS0_128:
326 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
327 reg |= 0x5;
328 break;
329 case CS0_64M_CS1_64M:
330 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
331 reg |= 0x1B;
332 break;
333 case CS0_64M_CS1_32M_CS2_32M:
334 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
335 reg |= 0x4B;
336 break;
337 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
338 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
339 reg |= 0x249;
340 break;
341 default:
342 printf("Unknown chip select size: %d\n", cs_size);
343 break;
344 }
345
346 writel(reg, &iomuxc_regs->gpr[1]);
347 }
348 #endif
349
350 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
351 /*
352 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
353 * defines a 2-bit SPEED_GRADING
354 */
355 #define OCOTP_TESTER3_SPEED_SHIFT 8
356 enum cpu_speed {
357 OCOTP_TESTER3_SPEED_GRADE0,
358 OCOTP_TESTER3_SPEED_GRADE1,
359 OCOTP_TESTER3_SPEED_GRADE2,
360 OCOTP_TESTER3_SPEED_GRADE3,
361 OCOTP_TESTER3_SPEED_GRADE4,
362 };
363
get_cpu_speed_grade_hz(void)364 u32 get_cpu_speed_grade_hz(void)
365 {
366 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
367 struct fuse_bank *bank = &ocotp->bank[1];
368 struct fuse_bank1_regs *fuse =
369 (struct fuse_bank1_regs *)bank->fuse_regs;
370 uint32_t val;
371
372 val = readl(&fuse->tester3);
373 val >>= OCOTP_TESTER3_SPEED_SHIFT;
374
375 if (is_imx8mn() || is_imx8mp()) {
376 val &= 0xf;
377 return 2300000000 - val * 100000000;
378 }
379
380 if (is_imx8mm())
381 val &= 0x7;
382 else
383 val &= 0x3;
384
385 switch(val) {
386 case OCOTP_TESTER3_SPEED_GRADE0:
387 return 800000000;
388 case OCOTP_TESTER3_SPEED_GRADE1:
389 return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
390 case OCOTP_TESTER3_SPEED_GRADE2:
391 return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
392 case OCOTP_TESTER3_SPEED_GRADE3:
393 return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
394 case OCOTP_TESTER3_SPEED_GRADE4:
395 return 2000000000;
396 }
397
398 return 0;
399 }
400
401 /*
402 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
403 * defines a 2-bit SPEED_GRADING
404 */
405 #define OCOTP_TESTER3_TEMP_SHIFT 6
406
407 /* iMX8MP uses OCOTP_TESTER3[6:5] for Market segment */
408 #define IMX8MP_OCOTP_TESTER3_TEMP_SHIFT 5
409
get_cpu_temp_grade(int * minc,int * maxc)410 u32 get_cpu_temp_grade(int *minc, int *maxc)
411 {
412 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
413 struct fuse_bank *bank = &ocotp->bank[1];
414 struct fuse_bank1_regs *fuse =
415 (struct fuse_bank1_regs *)bank->fuse_regs;
416 uint32_t val;
417
418 val = readl(&fuse->tester3);
419 if (is_imx8mp())
420 val >>= IMX8MP_OCOTP_TESTER3_TEMP_SHIFT;
421 else
422 val >>= OCOTP_TESTER3_TEMP_SHIFT;
423 val &= 0x3;
424
425 if (minc && maxc) {
426 if (val == TEMP_AUTOMOTIVE) {
427 *minc = -40;
428 *maxc = 125;
429 } else if (val == TEMP_INDUSTRIAL) {
430 *minc = -40;
431 *maxc = 105;
432 } else if (val == TEMP_EXTCOMMERCIAL) {
433 *minc = -20;
434 *maxc = 105;
435 } else {
436 *minc = 0;
437 *maxc = 95;
438 }
439 }
440 return val;
441 }
442 #endif
443
444 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
get_boot_device(void)445 enum boot_device get_boot_device(void)
446 {
447 struct bootrom_sw_info **p =
448 (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
449
450 enum boot_device boot_dev = SD1_BOOT;
451 u8 boot_type = (*p)->boot_dev_type;
452 u8 boot_instance = (*p)->boot_dev_instance;
453
454 switch (boot_type) {
455 case BOOT_TYPE_SD:
456 boot_dev = boot_instance + SD1_BOOT;
457 break;
458 case BOOT_TYPE_MMC:
459 boot_dev = boot_instance + MMC1_BOOT;
460 break;
461 case BOOT_TYPE_NAND:
462 boot_dev = NAND_BOOT;
463 break;
464 case BOOT_TYPE_QSPI:
465 boot_dev = QSPI_BOOT;
466 break;
467 case BOOT_TYPE_WEIM:
468 boot_dev = WEIM_NOR_BOOT;
469 break;
470 case BOOT_TYPE_SPINOR:
471 boot_dev = SPI_NOR_BOOT;
472 break;
473 case BOOT_TYPE_USB:
474 boot_dev = USB_BOOT;
475 break;
476 default:
477 #ifdef CONFIG_IMX8M
478 if (((readl(SRC_BASE_ADDR + 0x58) & 0x00007FFF) >> 12) == 0x4)
479 boot_dev = QSPI_BOOT;
480 #endif
481 break;
482 }
483
484 return boot_dev;
485 }
486 #endif
487
488 #ifdef CONFIG_NXP_BOARD_REVISION
nxp_board_rev(void)489 int nxp_board_rev(void)
490 {
491 /*
492 * Get Board ID information from OCOTP_GP1[15:8]
493 * RevA: 0x1
494 * RevB: 0x2
495 * RevC: 0x3
496 */
497 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
498 struct fuse_bank *bank = &ocotp->bank[4];
499 struct fuse_bank4_regs *fuse =
500 (struct fuse_bank4_regs *)bank->fuse_regs;
501
502 return (readl(&fuse->gp1) >> 8 & 0x0F);
503 }
504
nxp_board_rev_string(void)505 char nxp_board_rev_string(void)
506 {
507 const char *rev = "A";
508
509 return (*rev + nxp_board_rev() - 1);
510 }
511 #endif
512
reset_cpu(void)513 __weak void reset_cpu(void)
514 {
515 }
516