1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007
4 * Sascha Hauer, Pengutronix
5 *
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 */
8
9 #include <init.h>
10 #include <time.h>
11 #include <asm/io.h>
12 #include <div64.h>
13 #include <asm/global_data.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17
18 /* General purpose timers registers */
19 struct mxc_gpt {
20 unsigned int control;
21 unsigned int prescaler;
22 unsigned int status;
23 unsigned int nouse[6];
24 unsigned int counter;
25 };
26
27 static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
28
29 /* General purpose timers bitfields */
30 #define GPTCR_SWR (1 << 15) /* Software reset */
31 #define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */
32 #define GPTCR_FRR (1 << 9) /* Freerun / restart */
33 #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */
34 #define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
35 #define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */
36 #define GPTCR_CLKSOURCE_MASK (0x7 << 6)
37 #define GPTCR_TEN 1 /* Timer enable */
38
39 #define GPTPR_PRESCALER24M_SHIFT 12
40 #define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
41
42 DECLARE_GLOBAL_DATA_PTR;
43
gpt_has_clk_source_osc(void)44 static inline int gpt_has_clk_source_osc(void)
45 {
46 if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
47 is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
48 is_mx6ull() || is_mx6sll() || is_mx7())
49 return 1;
50
51 return 0;
52 }
53
gpt_get_clk(void)54 static inline ulong gpt_get_clk(void)
55 {
56 #ifdef CONFIG_MXC_GPT_HCLK
57 if (gpt_has_clk_source_osc())
58 return MXC_HCLK >> 3;
59 else
60 return mxc_get_clock(MXC_IPG_PERCLK);
61 #else
62 return MXC_CLK32;
63 #endif
64 }
65
timer_init(void)66 int timer_init(void)
67 {
68 int i;
69
70 /* setup GP Timer 1 */
71 __raw_writel(GPTCR_SWR, &cur_gpt->control);
72
73 /* We have no udelay by now */
74 for (i = 0; i < 100; i++)
75 __raw_writel(0, &cur_gpt->control);
76
77 i = __raw_readl(&cur_gpt->control);
78 i &= ~GPTCR_CLKSOURCE_MASK;
79
80 #ifdef CONFIG_MXC_GPT_HCLK
81 if (gpt_has_clk_source_osc()) {
82 i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
83
84 /*
85 * For DL/S, SX, UL, ULL, SLL set 24Mhz OSC
86 * Enable bit and prescaler
87 */
88 if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
89 is_mx6sll() || is_mx7()) {
90 i |= GPTCR_24MEN;
91
92 /* Produce 3Mhz clock */
93 __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT),
94 &cur_gpt->prescaler);
95 }
96 } else {
97 i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN;
98 }
99 #else
100 __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
101 i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
102 #endif
103 __raw_writel(i, &cur_gpt->control);
104
105 gd->arch.tbl = __raw_readl(&cur_gpt->counter);
106 gd->arch.tbu = 0;
107
108 return 0;
109 }
110
timer_read_counter(void)111 unsigned long timer_read_counter(void)
112 {
113 return __raw_readl(&cur_gpt->counter); /* current tick value */
114 }
115
116 /*
117 * This function is derived from PowerPC code (timebase clock frequency).
118 * On ARM it returns the number of timer ticks per second.
119 */
get_tbclk(void)120 ulong get_tbclk(void)
121 {
122 return gpt_get_clk();
123 }
124
125 /*
126 * This function is intended for SHORT delays only.
127 * It will overflow at around 10 seconds @ 400MHz,
128 * or 20 seconds @ 200MHz.
129 */
usec2ticks(unsigned long _usec)130 unsigned long usec2ticks(unsigned long _usec)
131 {
132 unsigned long long usec = _usec;
133
134 usec *= get_tbclk();
135 usec += 999999;
136 do_div(usec, 1000000);
137
138 return usec;
139 }
140